From c4153c1b15fa88796ce3bcccb49e3537c9e65ff3 Mon Sep 17 00:00:00 2001
From: Shobhit Srivastava <shobhit.srivastava@intel.com>
Date: Fri, 9 Oct 2015 17:05:16 +0530
Subject: Strago: Enable CA Mirror

Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
CA mirror is the Command Address mirroring option that is enabled
on this board

CQ-DEPEND=CL:13038

Original-Reviewed-on: https://chromium-review.googlesource.com/309190
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12749
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 src/mainboard/intel/strago/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/mainboard')

diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb
index ba8968c14c..91337878c2 100755
--- a/src/mainboard/intel/strago/devicetree.cb
+++ b/src/mainboard/intel/strago/devicetree.cb
@@ -13,6 +13,7 @@ chip soc/intel/braswell
 	register "PcdApertureSize" = "2"
 	register "PcdGttSize" = "1"
 	register "PcdDvfsEnable" = "0"
+	register "PcdCaMirrorEn" = "1"
 
 	############################################################
 	# Set the parameters for SiliconInit
-- 
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