From c2059fa72a654f8927f05bcecb4d98ef856c9b64 Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Wed, 26 Apr 2023 19:27:54 +0800 Subject: soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787 Reviewed-by: Matt DeVillier Reviewed-by: Jason Glenesk Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/mainboard/google/skyrim/variants/winterhold/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 4297f903b0..2e32b28919 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -112,8 +112,8 @@ chip soc/amd/mendocino register "dxio_tx_vboost_enable" = "1" - # The unit is set to one per 4ms - register "pwr_on_vary_bl_to_blon" = "0x1c" + # The unit is set to one per ms + register "edp_panel_t8_ms" = "112" device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. -- cgit v1.2.3