From c00f74a82c7b6eb42c0e4c3ca7604f0947cf0691 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Apr 2020 21:14:21 +0300 Subject: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M We should be sure that after romstage the pads will be configured according to the config from gpio.h only. This patch sets the GPIO configuration from gpio.h using the soc/intel/common/gpio.c driver again in ramstage. [1] https://review.coreboot.org/c/coreboot/+/40730 Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40735 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov --- src/mainboard/intel/cedarisland_crb/ramstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 src/mainboard/intel/cedarisland_crb/ramstage.c (limited to 'src/mainboard') diff --git a/src/mainboard/intel/cedarisland_crb/ramstage.c b/src/mainboard/intel/cedarisland_crb/ramstage.c new file mode 100644 index 0000000000..f4c716eda2 --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + /* configure Lewisburg PCH GPIO controller after FSP-M */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} -- cgit v1.2.3