From bfa29dc021f34f96bfe1f995e90834b0042a9784 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Sun, 9 Mar 2014 17:46:39 +1100 Subject: mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge. The platform dependent mainboard.c was incorrectly disabling the second clock signal feeding the GPP ports. This results in spurious hangs by calling the set_pcie_dereset() SB CIMx callback many times. This also stops coreboot from finding the second NIC behind the pci 15.0 bridge. Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5355 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering --- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index b17bc6a0be..44f9c48ee3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -65,11 +65,11 @@ static void mainboard_enable(device_t dev) acpi_slp_type = acpi_get_sleep_type(); #endif - /* enable GPP CLK0 thru CLK1 */ - /* disable GPP CLK2 thru SLT_GFX_CLK */ + /* enable GPP CLK0 thru CLK3 (interleaved) */ + /* disable GPP CLK4 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); *(misc_mem_clk_cntrl + 0) = 0xFF; - *(misc_mem_clk_cntrl + 1) = 0x00; + *(misc_mem_clk_cntrl + 1) = 0xFF; *(misc_mem_clk_cntrl + 2) = 0x00; *(misc_mem_clk_cntrl + 3) = 0x00; *(misc_mem_clk_cntrl + 4) = 0x00; -- cgit v1.2.3