From bccad8d0a851ebe60e0a861fcb5453bab139308f Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Mon, 4 Apr 2022 23:54:39 +0530 Subject: mb/intel/adlrvp: Configure the external V1p05/Vnn/VnnSx rails This patch configures external V1p05/Vnn/VnnSx rails for adlrvp-n to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: V Sowmya Change-Id: I06298eb1aec07eae34420c5736e912c707fefbc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63356 Tested-by: build bot (Jenkins) Reviewed-by: Usha P Reviewed-by: Maulik V Vaghela Reviewed-by: Sumeet R Pawnikar Reviewed-by: Kangheui Won --- src/mainboard/intel/adlrvp/devicetree_n.cb | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 40dba8b931..4fc655c9e9 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -136,6 +136,21 @@ chip soc/intel/alderlake }, }" + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + device domain 0 on device ref igpu on end device ref ipu on -- cgit v1.2.3