From bc89bc6680c186c3a7969e93f48b90bc6d6e9eb6 Mon Sep 17 00:00:00 2001 From: Bernardo Perez Priego Date: Tue, 5 Oct 2021 11:30:39 -0700 Subject: mb/intel/adlrvp_m: Enable retimer force power gpio Retimer FORCE_PWR GPIO is a debug GPIO, that has to be set LOW, to allow Retimer LC Domain to toggle during a switch from DP Alt to TBT Alt modes. Contrary to DS specifying it may be left unconfigured, hence floating, there are instances seen during boot, where it stays HIGH (adlmrvp) or LOW (adlprvp). Hence configure it to LOW. Branch=none Bug=none Test=Boot to OS, connect TBT dock which enumerates in DP Alt, Login, TBT dock enumerates in TBT Alt Signed-off-by: Bernardo Perez Priego Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58113 Tested-by: build bot (Jenkins) Reviewed-by: Bora Guvendik --- src/mainboard/intel/adlrvp/gpio_m.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 6f0568dbda..915b549e03 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -169,7 +169,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE), /* E3 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT) + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + + /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_E4, 0, DEEP) }; void variant_configure_gpio_pads(void) -- cgit v1.2.3