From b59991949580f59dbf0907881c7ea70729262e9a Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Fri, 9 Sep 2016 15:15:27 -0700 Subject: google/reef: Remove setting of GPIO_TIER1_SCI enable bit This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6 Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/16566 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/mainboard/google/reef/smihandler.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c index dbf9162266..fe4f8c4de3 100644 --- a/src/mainboard/google/reef/smihandler.c +++ b/src/mainboard/google/reef/smihandler.c @@ -38,9 +38,6 @@ void mainboard_smi_sleep(u8 slp_typ) pads = variant_sleep_gpio_table(&num); gpio_configure_pads(pads, num); - if (slp_typ == ACPI_S3) - enable_gpe(GPIO_TIER_1_SCI); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); -- cgit v1.2.3