From b21eaa74a656fa33f943f76ea0c53ca8374760f6 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 7 Mar 2013 15:23:45 -0800 Subject: ARMV7 and Google/Snow: Add exception support code to the ramstage This is previously used exception code from libpayload. On startup it installs and then tests an exception handler. The test is an unaligned memory operation. Yes, we've seen what might be exceptions in the ramstage, and it makes sense to handle them. This code is identical in structure and operation to the previously committed payload exception handler, though we reserve the right to change it as circumstances require. The remaining question is whether we need it in romstage. Change-Id: I24484686c33c9757af8ba171ebae9773828fb69d Signed-off-by: Gabe Black Signed-off-by: Ronald G. Minnich Reviewed-on: http://review.coreboot.org/2614 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/mainboard/google/snow/ramstage.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 9f259ef30e..be5216f2b7 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,6 +19,7 @@ #include #include +#include #include #include @@ -26,8 +27,10 @@ void hardwaremain(int boot_complete); void main(void) { console_init(); - printk(BIOS_INFO, "hello from ramstage\n"); + printk(BIOS_INFO, "hello from ramstage; now with deluxe exception handling.\n"); + /* this is going to move, but we must have it now and we're not sure where */ + exception_init(); /* place at top of physical memory */ high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; high_tables_base = CONFIG_SYS_SDRAM_BASE + -- cgit v1.2.3