From b0ac01b4c2c1be06b6618298b77c4a3b32d2411f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 5 May 2017 21:09:32 +0200 Subject: mb/intel/d510mo: Configure clockgen MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Configuring the clockgen like vendor bios fixes the issue where the display wobbles from left to right on the analog VGA output. Note: This seems to be common issue/requirement on Intel devices from that generation (also happens on dg43gt). TESTED on Intel D510MO. Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/19595 Reviewed-by: Sumeet R Pawnikar Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/intel/d510mo/romstage.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index c6406e6f9f..502d22078e 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -102,6 +102,9 @@ static void rcba_config(void) void mainboard_romstage_entry(unsigned long bist) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; + const u8 clockgen_block[13] = { 0x61, 0xd9, 0xfe, 0xff, 0xff, 0x00, + 0x00, 0x01, 0x03, 0x25, 0x83, 0x17, + 0x0d }; int cbmem_was_initted; int s3resume = 0; int boot_path; @@ -125,6 +128,8 @@ void mainboard_romstage_entry(unsigned long bist) report_bist_failure(bist); enable_smbus(); + smbus_block_write(0x69, 0, 13, clockgen_block); + pineview_early_initialization(); post_code(0x30); -- cgit v1.2.3