From afaa3d0356d5a518442701875505901e5806bb61 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Tue, 6 Oct 2020 15:50:21 -0700 Subject: trogdor: Modify DDR training to use mrc_cache Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table. BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots. Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/mainboard/google/trogdor/chromeos.fmd | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 1801d34318..d5324eee49 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -2,20 +2,19 @@ FLASH@0x0 8M { WP_RO 4M { - RO_SECTION 0x3c4000 { + RO_SECTION 0x3e4000 { BOOTBLOCK 96K COREBOOT(CBFS) - FMAP@0x3c0000 0x1000 + FMAP@0x3e0000 0x1000 GBB 0x2f00 RO_FRID 0x100 } RO_VPD(PRESERVE) - RO_DDR_TRAINING(PRESERVE) 8K } RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA -- cgit v1.2.3