From af879f2d34207b99bbb62e49a6e1bdcec4e217f4 Mon Sep 17 00:00:00 2001 From: Won Chung Date: Mon, 10 Apr 2023 20:52:55 +0000 Subject: mb/google/rex/var/rex0: Correct _PLD values for USB C0 Denote the correct value of ACPI _PLD for USB ports. The horizontal position of port C0 is incorrectly labelled. +----------------+ | | | Screen | | | +----------------+ C0 | | A0 | | C1 | | +----------------+ BUG=b:216490477 TEST=emerg-rex coreboot Signed-off-by: Won Chung Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74366 Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/rex/variants/rex0/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index ef517df2c4..59147c7ba4 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -278,7 +278,7 @@ chip soc/intel/meteorlake register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi @@ -319,7 +319,7 @@ chip soc/intel/meteorlake register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi -- cgit v1.2.3