From ab1b606fd485f26563ec8fb4c84bf22c13b65a02 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Tue, 25 May 2021 20:53:19 +0200
Subject: mb/amd/majolica: set PSPP policy to balanced

BUG=b:188793754

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54932
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/majolica/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mainboard')

diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb
index 0f540a151b..8f4fc9bfae 100644
--- a/src/mainboard/amd/majolica/devicetree.cb
+++ b/src/mainboard/amd/majolica/devicetree.cb
@@ -15,6 +15,8 @@ chip soc/amd/cezanne
 
 	register "s0ix_enable" = "true"
 
+	register "pspp_policy" = "DXIO_PSPP_BALANCED"
+
 	device domain 0 on
 		device ref gpp_gfx_bridge_0 on end # MXM
 		device ref gpp_bridge_0 on end # NVMe
-- 
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