From ab11f462191263e56ac539d532a365699d88b8f3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 29 Aug 2021 18:27:09 +0200 Subject: mb/razer/blade_stealth_kbl: Disable UART #0 in devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FSP-S disables UART #0 as per the `SerialIoDevMode` settings. Change-Id: Ic1f9f7ce6fd4f453200d563bd8556946eef1b287 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57225 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Mimoja --- src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 655a089189..42ee0c7971 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -214,7 +214,7 @@ chip soc/intel/skylake device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # Serial IO UART0 + device pci 1e.0 off end # Serial IO UART0 device pci 1e.6 off end # SDXC device pci 1f.0 on # LPC chip drivers/pc80/tpm -- cgit v1.2.3