From a7bc5b818a1eeb53dd59b81baf988228e110bcde Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 21 Dec 2020 03:46:58 +0100 Subject: mb/google/reef: do UART pad configuration at board-level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I279956f30cbb6fb031cdfe6aaa09b644b6b7d3e7 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49427 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/reef/bootblock.c | 6 +++++- src/mainboard/google/reef/variants/baseboard/gpio.c | 4 ++++ src/mainboard/google/reef/variants/coral/gpio.c | 4 ++++ 3 files changed, 13 insertions(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c index 577dae507d..0cbf3e62c2 100644 --- a/src/mainboard/google/reef/bootblock.c +++ b/src/mainboard/google/reef/bootblock.c @@ -6,12 +6,16 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); +} + +void bootblock_mainboard_init(void) +{ mainboard_ec_init(); } diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index aec2e988c9..6604a70cfe 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -354,6 +354,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ /* I2C2 - TPM */ diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index 29c41c68dc..01e4734e62 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -355,6 +355,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ /* I2C2 - TPM */ -- cgit v1.2.3