From 9abc91cc451af09dc90505ae9be2d4f43f796373 Mon Sep 17 00:00:00 2001 From: Roger Wang Date: Thu, 13 Jun 2024 10:40:29 +0800 Subject: mb/google/nissa/var/sundance: disable pcie port7 Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test. BUG=b:328147465 TEST=Build and check S0ix function and verify FAFT sleep funciton. Change-Id: I53f704ed11a5c63b5c079c6e60ce2fa32bbd8b1a Signed-off-by: Roger Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/83057 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Subrata Banik Reviewed-by: Eric Lai --- src/mainboard/google/brya/variants/sundance/overridetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb index 65d7e95cac..72cb317cb0 100644 --- a/src/mainboard/google/brya/variants/sundance/overridetree.cb +++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb @@ -273,6 +273,7 @@ chip soc/intel/alderlake device pci 00.0 on end end end + device ref pcie_rp7 off end device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] -- cgit v1.2.3