From 9a4d0dd3c26cc9514140979ab805f24260ecfa36 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Tue, 23 Feb 2021 18:30:43 +0300 Subject: mb/apple: start working on mbp8,2 --- src/mainboard/apple/macbookpro8_2/Kconfig | 38 ++++ src/mainboard/apple/macbookpro8_2/Kconfig.name | 2 + src/mainboard/apple/macbookpro8_2/Makefile.inc | 5 + src/mainboard/apple/macbookpro8_2/acpi/ec.asl | 9 + .../apple/macbookpro8_2/acpi/platform.asl | 10 + src/mainboard/apple/macbookpro8_2/acpi/superio.asl | 0 src/mainboard/apple/macbookpro8_2/acpi_tables.c | 13 ++ src/mainboard/apple/macbookpro8_2/board_info.txt | 6 + src/mainboard/apple/macbookpro8_2/cmos.default | 4 + src/mainboard/apple/macbookpro8_2/cmos.layout | 76 ++++++++ src/mainboard/apple/macbookpro8_2/devicetree.cb | 74 +++++++ src/mainboard/apple/macbookpro8_2/dsdt.asl | 27 +++ src/mainboard/apple/macbookpro8_2/early_init.c | 28 +++ .../apple/macbookpro8_2/gma-mainboard.ads | 22 +++ src/mainboard/apple/macbookpro8_2/gpio.c | 216 +++++++++++++++++++++ src/mainboard/apple/macbookpro8_2/hda_verb.c | 27 +++ src/mainboard/apple/macbookpro8_2/mainboard.c | 17 ++ 17 files changed, 574 insertions(+) create mode 100755 src/mainboard/apple/macbookpro8_2/Kconfig create mode 100755 src/mainboard/apple/macbookpro8_2/Kconfig.name create mode 100755 src/mainboard/apple/macbookpro8_2/Makefile.inc create mode 100755 src/mainboard/apple/macbookpro8_2/acpi/ec.asl create mode 100755 src/mainboard/apple/macbookpro8_2/acpi/platform.asl create mode 100755 src/mainboard/apple/macbookpro8_2/acpi/superio.asl create mode 100755 src/mainboard/apple/macbookpro8_2/acpi_tables.c create mode 100755 src/mainboard/apple/macbookpro8_2/board_info.txt create mode 100644 src/mainboard/apple/macbookpro8_2/cmos.default create mode 100644 src/mainboard/apple/macbookpro8_2/cmos.layout create mode 100755 src/mainboard/apple/macbookpro8_2/devicetree.cb create mode 100755 src/mainboard/apple/macbookpro8_2/dsdt.asl create mode 100755 src/mainboard/apple/macbookpro8_2/early_init.c create mode 100755 src/mainboard/apple/macbookpro8_2/gma-mainboard.ads create mode 100755 src/mainboard/apple/macbookpro8_2/gpio.c create mode 100755 src/mainboard/apple/macbookpro8_2/hda_verb.c create mode 100755 src/mainboard/apple/macbookpro8_2/mainboard.c (limited to 'src/mainboard') diff --git a/src/mainboard/apple/macbookpro8_2/Kconfig b/src/mainboard/apple/macbookpro8_2/Kconfig new file mode 100755 index 0000000000..4367270bcc --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/Kconfig @@ -0,0 +1,38 @@ +if BOARD_APPLE_MACBOOKPRO8_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default "apple/macbookpro8_2" + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro8,2" + +config VGA_BIOS_ID + string + default "8086,0126" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/apple/macbookpro8_2/Kconfig.name b/src/mainboard/apple/macbookpro8_2/Kconfig.name new file mode 100755 index 0000000000..18977f5759 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO8_2 + bool "MacBookPro8,2" diff --git a/src/mainboard/apple/macbookpro8_2/Makefile.inc b/src/mainboard/apple/macbookpro8_2/Makefile.inc new file mode 100755 index 0000000000..18391d8b18 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro8_2/acpi/ec.asl b/src/mainboard/apple/macbookpro8_2/acpi/ec.asl new file mode 100755 index 0000000000..75f766bdb9 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/acpi/ec.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define LIDS_OFFSET 0x60 +#define HPAC_OFFSET 0x60 +#define WKLD_OFFSET 0x68 + +#include +#include +#include diff --git a/src/mainboard/apple/macbookpro8_2/acpi/platform.asl b/src/mainboard/apple/macbookpro8_2/acpi/platform.asl new file mode 100755 index 0000000000..aff432b6f4 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/apple/macbookpro8_2/acpi/superio.asl b/src/mainboard/apple/macbookpro8_2/acpi/superio.asl new file mode 100755 index 0000000000..e69de29bb2 diff --git a/src/mainboard/apple/macbookpro8_2/acpi_tables.c b/src/mainboard/apple/macbookpro8_2/acpi_tables.c new file mode 100755 index 0000000000..ad1295b6b3 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/acpi_tables.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro8_2/board_info.txt b/src/mainboard/apple/macbookpro8_2/board_info.txt new file mode 100755 index 0000000000..8e0e321640 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2011 diff --git a/src/mainboard/apple/macbookpro8_2/cmos.default b/src/mainboard/apple/macbookpro8_2/cmos.default new file mode 100644 index 0000000000..d0e926c952 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/cmos.default @@ -0,0 +1,4 @@ +debug_level=Debug +hybrid_graphics_mode=Integrated Only +gfx_uma_size=32M +me_state=Normal diff --git a/src/mainboard/apple/macbookpro8_2/cmos.layout b/src/mainboard/apple/macbookpro8_2/cmos.layout new file mode 100644 index 0000000000..4172d68834 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/cmos.layout @@ -0,0 +1,76 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: ME +425 1 e 13 me_state +426 2 h 0 me_state_prev + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +13 0 Normal +13 1 Disabled + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/apple/macbookpro8_2/devicetree.cb b/src/mainboard/apple/macbookpro8_2/devicetree.cb new file mode 100755 index 0000000000..1d6d75e901 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/devicetree.cb @@ -0,0 +1,74 @@ +chip northbridge/intel/sandybridge + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + register "gpu_cpu_backlight" = "0x00000710" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "3000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "110" + register "gpu_panel_power_up_delay" = "110" + register "gpu_pch_backlight" = "0x07100710" + + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + device lapic 0x0 on end + device lapic 0xacac off end + end + end + + device domain 0x0 on + subsystemid 0x8086 0x7270 inherit + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00dc + end + device pci 01.0 on # PEG + subsystemid 0x106b 0x00dc + end + device pci 02.0 on # iGPU + subsystemid 0x106b 0x00dc + end + device pci 1a.7 on end + device pci 1d.7 on end + device pci 01.1 on + subsystemid 0x106b 0x00dc + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x5" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 Unsupported PCI device 8086:1c2c + device pci 1b.0 on end # High Definition end Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 Unsupported PCI device 8086:1c27 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Con endtroller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Con endtroller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/apple/macbookpro8_2/dsdt.asl b/src/mainboard/apple/macbookpro8_2/dsdt.asl new file mode 100755 index 0000000000..9a7d54b963 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include + #include "acpi/platform.asl" + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } +} diff --git a/src/mainboard/apple/macbookpro8_2/early_init.c b/src/mainboard/apple/macbookpro8_2/early_init.c new file mode 100755 index 0000000000..7e656a7265 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/early_init.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, /* USB HUB 1 */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ + { 1, 0, -1 }, /* USB HUB 2 */ + { 1, 0, -1 }, /* Camera */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/apple/macbookpro8_2/gma-mainboard.ads b/src/mainboard/apple/macbookpro8_2/gma-mainboard.ads new file mode 100755 index 0000000000..6a8ef6b09b --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + LVDS, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookpro8_2/gpio.c b/src/mainboard/apple/macbookpro8_2/gpio.c new file mode 100755 index 0000000000..3a2e776b42 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/gpio.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio16 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro8_2/hda_verb.c b/src/mainboard/apple/macbookpro8_2/hda_verb.c new file mode 100755 index 0000000000..2fbe1ce033 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/hda_verb.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b1d00, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0, 0x106b1d00), + AZALIA_PIN_CFG(0, 0x09, 0x002b4050), + AZALIA_PIN_CFG(0, 0x0a, 0x90100141), + AZALIA_PIN_CFG(0, 0x0b, 0x90100140), + AZALIA_PIN_CFG(0, 0x0c, 0x008b3020), + AZALIA_PIN_CFG(0, 0x0d, 0x90a00110), + AZALIA_PIN_CFG(0, 0x0e, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x00cbe030), + AZALIA_PIN_CFG(0, 0x10, 0x004be060), + AZALIA_PIN_CFG(0, 0x12, 0x400000f0), + AZALIA_PIN_CFG(0, 0x15, 0x400000f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro8_2/mainboard.c b/src/mainboard/apple/macbookpro8_2/mainboard.c new file mode 100755 index 0000000000..4322c1e019 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_2/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- cgit v1.2.3