From 99c4a29cdc13418b05945af05dae635c1058c0f3 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 4 Aug 2021 19:28:45 +0200 Subject: mb/pcengines/apu2/gpio_ftns.h: add comment about GPIO numbers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mapping of the package GPIO numbers to the GPIO numbers on the GPIO controller isn't a 1:1 one, so add a comment about that to avoid confusion. Also change the comment style to match the style guide. Signed-off-by: Felix Held Change-Id: Ie30bf5483ea2e2516d7e3fdd21ea9338362e526e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56808 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/pcengines/apu2/gpio_ftns.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 95c744f62b..638622076e 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -5,11 +5,12 @@ int get_spd_offset(void); -// -// Based on PC Engines APU2C and APU3A schematics -// http://www.pcengines.ch/schema/apu2c.pdf -// http://www.pcengines.ch/schema/apu3a.pdf -// +/* + * Based on PC Engines APU2C and APU3A schematics + * http://www.pcengines.ch/schema/apu2c.pdf + * http://www.pcengines.ch/schema/apu3a.pdf + * Beware that the GPIO pin numbers on the package don't match the internal GPIO numbers + */ #define GPIO_22 0x09 // MODESW (APU5) #define GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5) #define GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5) -- cgit v1.2.3