From 98689df18f7431c69cc0b53a53d083ab3cef28ce Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 6 Nov 2018 14:59:11 +0100 Subject: siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason we have to adjust the PIR6 register (0x314c) which is responsible for PCIe device 13h and 14h. This means that the interrupt routing will also be the same for both PCIe devices. The bridge is connected to PCIe root port 2 and 3 over two lanes (Device 13.0 and 13.1). The following routing is required: INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC# Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/29513 Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index ccf3ab8ec1..ade923a65e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -32,11 +32,10 @@ void variant_mainboard_final(void) { struct device *dev = NULL; - /* - * PIR6 register mapping for PCIe root ports - * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# + /* PIR6 register mapping for PCIe root ports + * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# */ - pcr_write16(PID_ITSS, 0x314c, 0x0321); + pcr_write16(PID_ITSS, 0x314c, 0x2103); /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); -- cgit v1.2.3