From 9484792ad1470117aeb9bd234adc86f7e9087b0b Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Fri, 15 Nov 2019 14:42:07 +0800
Subject: mb/google/drallion/variants/drallion: Update thermal configuration
 for DPTF

Follow thermal table for first tuning.

BUG=b:144464314
TEST=Built and tested on drallion

Change-Id: I4546622cdc6efb2bf2eb973cfc5c6f22c40cc6ef
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36860
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../drallion/include/variant/acpi/dptf.asl         | 36 +++++++++++-----------
 1 file changed, 18 insertions(+), 18 deletions(-)

(limited to 'src/mainboard')

diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl
index 73e1decc1b..4ecdf1a67e 100644
--- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl
@@ -13,42 +13,42 @@
  * GNU General Public License for more details.
  */
 
-#define DPTF_CPU_PASSIVE	98
-#define DPTF_CPU_CRITICAL	108
+#define DPTF_CPU_PASSIVE	99
+#define DPTF_CPU_CRITICAL	127
 
 /* Skin Sensor for CPU VR temperature monitor */
 #define DPTF_TSR0_SENSOR_ID	1
 #define DPTF_TSR0_SENSOR_NAME	"Skin"
-#define DPTF_TSR0_PASSIVE	55
-#define DPTF_TSR0_CRITICAL	100
+#define DPTF_TSR0_PASSIVE	64
+#define DPTF_TSR0_CRITICAL	127
 
 /* Memory Sensor for DDR temperature monitor */
 #define DPTF_TSR1_SENSOR_ID	2
 #define DPTF_TSR1_SENSOR_NAME	"DDR"
-#define DPTF_TSR1_PASSIVE	53
-#define DPTF_TSR1_CRITICAL	100
+#define DPTF_TSR1_PASSIVE	54
+#define DPTF_TSR1_CRITICAL	127
 
 /* M.2 Sensor for Ambient temperature monitor */
 #define DPTF_TSR2_SENSOR_ID	3
 #define DPTF_TSR2_SENSOR_NAME	"Ambient"
-#define DPTF_TSR2_PASSIVE	38
-#define DPTF_TSR2_CRITICAL	93
+#define DPTF_TSR2_PASSIVE	40
+#define DPTF_TSR2_CRITICAL	127
 
 #undef DPTF_ENABLE_FAN_CONTROL
 #undef DPTF_ENABLE_CHARGER
 
 Name (DTRT, Package () {
 	/* CPU Throttle Effect on CPU */
-	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 250, 10, 0, 0, 0, 0 },
 
 	/* CPU Throttle Effect on Skin (TSR0) */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 250, 10, 0, 0, 0, 0 },
 
 	/* CPU Throttle Effect on DDR (TSR1) */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 250, 10, 2, 0, 0, 0 },
 
 	/* CPU Throttle Effect on Ambient (TSR2) */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 250, 10, 1, 0, 0, 0 },
 })
 
 Name (MPPC, Package ()
@@ -56,18 +56,18 @@ Name (MPPC, Package ()
 	0x2,		/* Revision */
 	Package () {	/* Power Limit 1 */
 		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		3000,	/* PowerLimitMinimum */
-		21000,	/* PowerLimitMaximum */
-		28000,	/* TimeWindowMinimum */
-		28000,	/* TimeWindowMaximum */
+		4000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		100000,	/* TimeWindowMinimum */
+		100000,	/* TimeWindowMaximum */
 		100	/* StepSize */
 	},
 	Package () {	/* Power Limit 2 */
 		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
 		15000,	/* PowerLimitMinimum */
 		51000,	/* PowerLimitMaximum */
-		28000,	/* TimeWindowMinimum */
-		28000,	/* TimeWindowMaximum */
+		280000,	/* TimeWindowMinimum */
+		280000,	/* TimeWindowMaximum */
 		100	/* StepSize */
 	}
 })
-- 
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