From 939cabfae43661b75fb109bd8f280aee0a99ec7e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 29 Apr 2020 17:45:57 -0500 Subject: mb/purism/librem_skl: drop SataSpeedLimit restriction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SataSpeedLimit was set to 3Gbps to work around issues which are now known to be the result of incorrect FSP behavior. Since SataPwrOptEnable is now set at the SoC level and ensures the SIR registers are correctly programmed, we can re-enable 6Gbps operation without errors. Test: build/boot Librem 13v2 with both m.2 and 2.5" SATA drives, check dmesg for errors. Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/40909 Reviewed-by: Paul Menzel Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb | 1 - src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb | 1 - 2 files changed, 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 6c55af66cc..b15dc2df2e 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -54,7 +54,6 @@ chip soc/intel/skylake register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "SataSpeedLimit" = "2" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index f48135297e..d273462c97 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -54,7 +54,6 @@ chip soc/intel/skylake register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "SataSpeedLimit" = "2" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" -- cgit v1.2.3