From 90eca855960e9ae49c0218e47aa0f5655157ac9c Mon Sep 17 00:00:00 2001 From: Tarun Tuli Date: Wed, 24 Aug 2022 23:47:14 -0400 Subject: mb/google/rex: Update DQS for Rex Update the DQS for Rex as per the latest Rex schematics (08/25). BUG=b:243734885 TEST=Built successfully. Confirmed on HW. Change-Id: I2a458a3da725f953cbba8a194ac6f314f5467419 Signed-off-by: Tarun Tuli Reviewed-on: https://review.coreboot.org/c/coreboot/+/67041 Reviewed-by: Kapil Porwal Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Maulik Vaghela Reviewed-by: Ivy Jian --- src/mainboard/google/rex/variants/baseboard/rex/memory.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/rex/variants/baseboard/rex/memory.c b/src/mainboard/google/rex/variants/baseboard/rex/memory.c index 9eaef9559a..1541cec950 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/memory.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/memory.c @@ -50,14 +50,14 @@ static const struct mb_cfg baseboard_memcfg = { /* DQS CPU<>DRAM map */ .lpx_dqs_map = { - .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, }, .lp5x_config = { -- cgit v1.2.3