From 8d3f419cbc345884aedd7a2f9c1b5bcf378dcefd Mon Sep 17 00:00:00 2001 From: Robert Chen Date: Tue, 5 Nov 2024 21:00:20 -0500 Subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements. BUG=b:377400590 TEST=Tested on Drawman with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 BRANCH=firmware-dedede-13606.B Signed-off-by: Robert Chen Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/85011 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/drawcia/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 67c9262007..6c745d9f97 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -7,6 +7,9 @@ fw_config end chip soc/intel/jasperlake + # PCIe RP LTR configuration + register "PcieRpLtrEnable[7]" = "1" + # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera -- cgit v1.2.3