From 8bd6bd26eda8eefd9b87a3a0572af27f75360b9a Mon Sep 17 00:00:00 2001 From: Barnali Sarkar Date: Fri, 18 Dec 2015 15:53:08 +0530 Subject: google/lars: Enable FspSkipMpInit token MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in Lars with SkipMpInit enabled from CB CQ-DEPEND=CL:319353 Change-Id: Ib35d9072b883592d22466dfeb1fd45403c0479d4 Signed-off-by: Patrick Georgi Original-Commit-Id: 91cf59ea7865568eca2ce242d81c4c486076d5ac Original-Change-Id: Ibb46fc6bc7e862c9ea8bc9f9b0d508c3707282a2 Original-Signed-off-by: Barnali Sarkar Original-Reviewed-on: https://chromium-review.googlesource.com/319257 Original-Reviewed-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/12999 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/lars/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 7cf2ac8b0f..ed47820f39 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -30,6 +30,7 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" + register "FspSkipMpInit" = "1" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s -- cgit v1.2.3