From 88e71e88597d939972267cdb00aca3cc61f5e171 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 2 May 2009 12:42:30 +0000 Subject: Run dos2unix on all files: find . -type f| grep -v svn | xargs dos2unix Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/asus/m2v-mx_se/Options.lb | 2 +- src/mainboard/dell/s1850/irq_tables.c | 96 +++++------ src/mainboard/msi/ms9185/Options.lb | 2 +- src/mainboard/msi/ms9282/Options.lb | 4 +- src/mainboard/rca/rm4100/gpio.c | 286 ++++++++++++++++---------------- src/mainboard/thomson/ip1000/gpio.c | 286 ++++++++++++++++---------------- 6 files changed, 338 insertions(+), 338 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb index 93c1bd32e6..5d74fbce22 100644 --- a/src/mainboard/asus/m2v-mx_se/Options.lb +++ b/src/mainboard/asus/m2v-mx_se/Options.lb @@ -94,7 +94,7 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY uses SB_HT_CHAIN_ON_BUS0 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_USE_PRINTK_IN_CAR +uses CONFIG_USE_PRINTK_IN_CAR default ROM_SIZE = 512 * 1024 default FALLBACK_SIZE = 256 * 1024 diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c index d0e7be1cd9..dc5514bbac 100644 --- a/src/mainboard/dell/s1850/irq_tables.c +++ b/src/mainboard/dell/s1850/irq_tables.c @@ -1,48 +1,48 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up - * - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - -#include - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*17, /* there can be total 17 devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x24d0, /* Device */ - 0, /* Crap (miniport) */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xc4, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x02<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x04<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x05<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x06<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x05,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0}, - {0x01,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0}, - {0x00,(0x1d<<3)|0x0, {{0x60, 0xccf8}, {0x63, 0xccf8}, {0x62, 0xccf8}, {0x6b, 0x0ccf8}}, 0x0, 0x0}, - {0x09,(0x05<<3)|0x0, {{0x68, 0xccf8}, {0x69, 0xccf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x09,(0x06<<3)|0x0, {{0x6b, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x09,(0x0d<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x09,(0x03<<3)|0x0, {{0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0}, - {0x06,(0x07<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x07,(0x08<<3)|0x0, {{0x61, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x02,(0x05<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x04,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x1, 0x0}, - {0x08,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x2, 0x0}, - {0x02,(0x0e<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr); -} - +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up + * + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*17, /* there can be total 17 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x24d0, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xc4, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x02<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x04<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x05<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x00,(0x06<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x05,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0}, + {0x01,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0}, + {0x00,(0x1d<<3)|0x0, {{0x60, 0xccf8}, {0x63, 0xccf8}, {0x62, 0xccf8}, {0x6b, 0x0ccf8}}, 0x0, 0x0}, + {0x09,(0x05<<3)|0x0, {{0x68, 0xccf8}, {0x69, 0xccf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x09,(0x06<<3)|0x0, {{0x6b, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x09,(0x0d<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x09,(0x03<<3)|0x0, {{0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0}, + {0x06,(0x07<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x07,(0x08<<3)|0x0, {{0x61, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x02,(0x05<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + {0x04,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x1, 0x0}, + {0x08,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x2, 0x0}, + {0x02,(0x0e<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} + diff --git a/src/mainboard/msi/ms9185/Options.lb b/src/mainboard/msi/ms9185/Options.lb index efd5dc95bc..5c3073e2d2 100644 --- a/src/mainboard/msi/ms9185/Options.lb +++ b/src/mainboard/msi/ms9185/Options.lb @@ -220,7 +220,7 @@ default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcc000 default DCACHE_RAM_SIZE=0x04000 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb index a666a8c61e..1a686826cd 100644 --- a/src/mainboard/msi/ms9282/Options.lb +++ b/src/mainboard/msi/ms9282/Options.lb @@ -100,7 +100,7 @@ uses SB_HT_CHAIN_ON_BUS0 uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_USE_PRINTK_IN_CAR +uses CONFIG_USE_PRINTK_IN_CAR ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes @@ -265,7 +265,7 @@ default CONFIG_GDB_STUB=0 ## The Serial Console ## default CONFIG_USE_PRINTK_IN_CAR=1 - + # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c index 97231e52a0..d51bc90e78 100644 --- a/src/mainboard/rca/rm4100/gpio.c +++ b/src/mainboard/rca/rm4100/gpio.c @@ -1,143 +1,143 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Joseph Smith - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define PME_DEV PNP_DEV(0x2e, 0x0a) -#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ -#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */ - -/* Early mainboard specific GPIO setup. */ -static void mb_gpio_init(void) -{ - device_t dev; - uint16_t port; - uint32_t set_gpio; - - /* Southbridge GPIOs. */ - /* Set the LPC device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); - - /* Set GPIO23 to high, this enables the LAN controller. */ - udelay(10); - set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c); - set_gpio |= 1 << 23; - outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c); - - /* Super I/O GPIOs. */ - dev = PME_DEV; - port = dev >> 8; - - /* Enter the configuration state. */ - outb(0x55, port); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); - pnp_set_enable(dev, 1); - - /* GP21 - LED_RED */ - outl(0x01, PME_IO_BASE_ADDR + 0x2c); - - /* GP30 - FAN2_TACH */ - outl(0x05, PME_IO_BASE_ADDR + 0x33); - - /* GP31 - FAN1_TACH */ - outl(0x05, PME_IO_BASE_ADDR + 0x34); - - /* GP32 - FAN2_CTRL */ - outl(0x04, PME_IO_BASE_ADDR + 0x35); - - /* GP33 - FAN1_CTRL */ - outl(0x04, PME_IO_BASE_ADDR + 0x36); - - /* GP34 - AUD_MUTE_OUT_R */ - outl(0x00, PME_IO_BASE_ADDR + 0x37); - - /* GP36 - KBRST */ - outl(0x00, PME_IO_BASE_ADDR + 0x39); - - /* GP37 - A20GATE */ - outl(0x00, PME_IO_BASE_ADDR + 0x3a); - - /* GP42 - GPIO_PME_OUT */ - outl(0x00, PME_IO_BASE_ADDR + 0x3d); - - /* GP50 - SER2_RI */ - outl(0x05, PME_IO_BASE_ADDR + 0x3f); - - /* GP51 - SER2_DCD */ - outl(0x05, PME_IO_BASE_ADDR + 0x40); - - /* GP52 - SER2_RX */ - outl(0x05, PME_IO_BASE_ADDR + 0x41); - - /* GP53 - SER2_TX */ - outl(0x04, PME_IO_BASE_ADDR + 0x42); - - /* GP55 - SER2_RTS */ - outl(0x04, PME_IO_BASE_ADDR + 0x44); - - /* GP56 - SER2_CTS */ - outl(0x05, PME_IO_BASE_ADDR + 0x45); - - /* GP57 - SER2_DTR */ - outl(0x04, PME_IO_BASE_ADDR + 0x46); - - /* GP60 - LED_GREEN */ - outl(0x01, PME_IO_BASE_ADDR + 0x47); - - /* GP61 - LED_YELLOW */ - outl(0x01, PME_IO_BASE_ADDR + 0x48); - - /* GP3 */ - outl(0xc0, PME_IO_BASE_ADDR + 0x4d); - - /* GP4 */ - outl(0x04, PME_IO_BASE_ADDR + 0x4e); - - /* FAN1 */ - outl(0x01, PME_IO_BASE_ADDR + 0x56); - - /* FAN2 */ - outl(0x01, PME_IO_BASE_ADDR + 0x57); - - /* Fan Control */ - outl(0x50, PME_IO_BASE_ADDR + 0x58); - - /* Fan1 Tachometer */ - outl(0xff, PME_IO_BASE_ADDR + 0x59); - - /* Fan2 Tachometer */ - outl(0xff, PME_IO_BASE_ADDR + 0x5a); - - /* LED1 */ - outl(0x00, PME_IO_BASE_ADDR + 0x5d); - - /* LED2 */ - outl(0x00, PME_IO_BASE_ADDR + 0x5e); - - /* Keyboard Scan Code */ - outl(0x00, PME_IO_BASE_ADDR + 0x5f); - - /* Exit the configuration state. */ - outb(0xaa, port); -} +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define PME_DEV PNP_DEV(0x2e, 0x0a) +#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ +#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */ + +/* Early mainboard specific GPIO setup. */ +static void mb_gpio_init(void) +{ + device_t dev; + uint16_t port; + uint32_t set_gpio; + + /* Southbridge GPIOs. */ + /* Set the LPC device statically. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + + /* Set GPIO23 to high, this enables the LAN controller. */ + udelay(10); + set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c); + set_gpio |= 1 << 23; + outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c); + + /* Super I/O GPIOs. */ + dev = PME_DEV; + port = dev >> 8; + + /* Enter the configuration state. */ + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); + pnp_set_enable(dev, 1); + + /* GP21 - LED_RED */ + outl(0x01, PME_IO_BASE_ADDR + 0x2c); + + /* GP30 - FAN2_TACH */ + outl(0x05, PME_IO_BASE_ADDR + 0x33); + + /* GP31 - FAN1_TACH */ + outl(0x05, PME_IO_BASE_ADDR + 0x34); + + /* GP32 - FAN2_CTRL */ + outl(0x04, PME_IO_BASE_ADDR + 0x35); + + /* GP33 - FAN1_CTRL */ + outl(0x04, PME_IO_BASE_ADDR + 0x36); + + /* GP34 - AUD_MUTE_OUT_R */ + outl(0x00, PME_IO_BASE_ADDR + 0x37); + + /* GP36 - KBRST */ + outl(0x00, PME_IO_BASE_ADDR + 0x39); + + /* GP37 - A20GATE */ + outl(0x00, PME_IO_BASE_ADDR + 0x3a); + + /* GP42 - GPIO_PME_OUT */ + outl(0x00, PME_IO_BASE_ADDR + 0x3d); + + /* GP50 - SER2_RI */ + outl(0x05, PME_IO_BASE_ADDR + 0x3f); + + /* GP51 - SER2_DCD */ + outl(0x05, PME_IO_BASE_ADDR + 0x40); + + /* GP52 - SER2_RX */ + outl(0x05, PME_IO_BASE_ADDR + 0x41); + + /* GP53 - SER2_TX */ + outl(0x04, PME_IO_BASE_ADDR + 0x42); + + /* GP55 - SER2_RTS */ + outl(0x04, PME_IO_BASE_ADDR + 0x44); + + /* GP56 - SER2_CTS */ + outl(0x05, PME_IO_BASE_ADDR + 0x45); + + /* GP57 - SER2_DTR */ + outl(0x04, PME_IO_BASE_ADDR + 0x46); + + /* GP60 - LED_GREEN */ + outl(0x01, PME_IO_BASE_ADDR + 0x47); + + /* GP61 - LED_YELLOW */ + outl(0x01, PME_IO_BASE_ADDR + 0x48); + + /* GP3 */ + outl(0xc0, PME_IO_BASE_ADDR + 0x4d); + + /* GP4 */ + outl(0x04, PME_IO_BASE_ADDR + 0x4e); + + /* FAN1 */ + outl(0x01, PME_IO_BASE_ADDR + 0x56); + + /* FAN2 */ + outl(0x01, PME_IO_BASE_ADDR + 0x57); + + /* Fan Control */ + outl(0x50, PME_IO_BASE_ADDR + 0x58); + + /* Fan1 Tachometer */ + outl(0xff, PME_IO_BASE_ADDR + 0x59); + + /* Fan2 Tachometer */ + outl(0xff, PME_IO_BASE_ADDR + 0x5a); + + /* LED1 */ + outl(0x00, PME_IO_BASE_ADDR + 0x5d); + + /* LED2 */ + outl(0x00, PME_IO_BASE_ADDR + 0x5e); + + /* Keyboard Scan Code */ + outl(0x00, PME_IO_BASE_ADDR + 0x5f); + + /* Exit the configuration state. */ + outb(0xaa, port); +} diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c index 97231e52a0..d51bc90e78 100644 --- a/src/mainboard/thomson/ip1000/gpio.c +++ b/src/mainboard/thomson/ip1000/gpio.c @@ -1,143 +1,143 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Joseph Smith - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define PME_DEV PNP_DEV(0x2e, 0x0a) -#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ -#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */ - -/* Early mainboard specific GPIO setup. */ -static void mb_gpio_init(void) -{ - device_t dev; - uint16_t port; - uint32_t set_gpio; - - /* Southbridge GPIOs. */ - /* Set the LPC device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); - - /* Set GPIO23 to high, this enables the LAN controller. */ - udelay(10); - set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c); - set_gpio |= 1 << 23; - outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c); - - /* Super I/O GPIOs. */ - dev = PME_DEV; - port = dev >> 8; - - /* Enter the configuration state. */ - outb(0x55, port); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); - pnp_set_enable(dev, 1); - - /* GP21 - LED_RED */ - outl(0x01, PME_IO_BASE_ADDR + 0x2c); - - /* GP30 - FAN2_TACH */ - outl(0x05, PME_IO_BASE_ADDR + 0x33); - - /* GP31 - FAN1_TACH */ - outl(0x05, PME_IO_BASE_ADDR + 0x34); - - /* GP32 - FAN2_CTRL */ - outl(0x04, PME_IO_BASE_ADDR + 0x35); - - /* GP33 - FAN1_CTRL */ - outl(0x04, PME_IO_BASE_ADDR + 0x36); - - /* GP34 - AUD_MUTE_OUT_R */ - outl(0x00, PME_IO_BASE_ADDR + 0x37); - - /* GP36 - KBRST */ - outl(0x00, PME_IO_BASE_ADDR + 0x39); - - /* GP37 - A20GATE */ - outl(0x00, PME_IO_BASE_ADDR + 0x3a); - - /* GP42 - GPIO_PME_OUT */ - outl(0x00, PME_IO_BASE_ADDR + 0x3d); - - /* GP50 - SER2_RI */ - outl(0x05, PME_IO_BASE_ADDR + 0x3f); - - /* GP51 - SER2_DCD */ - outl(0x05, PME_IO_BASE_ADDR + 0x40); - - /* GP52 - SER2_RX */ - outl(0x05, PME_IO_BASE_ADDR + 0x41); - - /* GP53 - SER2_TX */ - outl(0x04, PME_IO_BASE_ADDR + 0x42); - - /* GP55 - SER2_RTS */ - outl(0x04, PME_IO_BASE_ADDR + 0x44); - - /* GP56 - SER2_CTS */ - outl(0x05, PME_IO_BASE_ADDR + 0x45); - - /* GP57 - SER2_DTR */ - outl(0x04, PME_IO_BASE_ADDR + 0x46); - - /* GP60 - LED_GREEN */ - outl(0x01, PME_IO_BASE_ADDR + 0x47); - - /* GP61 - LED_YELLOW */ - outl(0x01, PME_IO_BASE_ADDR + 0x48); - - /* GP3 */ - outl(0xc0, PME_IO_BASE_ADDR + 0x4d); - - /* GP4 */ - outl(0x04, PME_IO_BASE_ADDR + 0x4e); - - /* FAN1 */ - outl(0x01, PME_IO_BASE_ADDR + 0x56); - - /* FAN2 */ - outl(0x01, PME_IO_BASE_ADDR + 0x57); - - /* Fan Control */ - outl(0x50, PME_IO_BASE_ADDR + 0x58); - - /* Fan1 Tachometer */ - outl(0xff, PME_IO_BASE_ADDR + 0x59); - - /* Fan2 Tachometer */ - outl(0xff, PME_IO_BASE_ADDR + 0x5a); - - /* LED1 */ - outl(0x00, PME_IO_BASE_ADDR + 0x5d); - - /* LED2 */ - outl(0x00, PME_IO_BASE_ADDR + 0x5e); - - /* Keyboard Scan Code */ - outl(0x00, PME_IO_BASE_ADDR + 0x5f); - - /* Exit the configuration state. */ - outb(0xaa, port); -} +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define PME_DEV PNP_DEV(0x2e, 0x0a) +#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ +#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */ + +/* Early mainboard specific GPIO setup. */ +static void mb_gpio_init(void) +{ + device_t dev; + uint16_t port; + uint32_t set_gpio; + + /* Southbridge GPIOs. */ + /* Set the LPC device statically. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + + /* Set GPIO23 to high, this enables the LAN controller. */ + udelay(10); + set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c); + set_gpio |= 1 << 23; + outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c); + + /* Super I/O GPIOs. */ + dev = PME_DEV; + port = dev >> 8; + + /* Enter the configuration state. */ + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); + pnp_set_enable(dev, 1); + + /* GP21 - LED_RED */ + outl(0x01, PME_IO_BASE_ADDR + 0x2c); + + /* GP30 - FAN2_TACH */ + outl(0x05, PME_IO_BASE_ADDR + 0x33); + + /* GP31 - FAN1_TACH */ + outl(0x05, PME_IO_BASE_ADDR + 0x34); + + /* GP32 - FAN2_CTRL */ + outl(0x04, PME_IO_BASE_ADDR + 0x35); + + /* GP33 - FAN1_CTRL */ + outl(0x04, PME_IO_BASE_ADDR + 0x36); + + /* GP34 - AUD_MUTE_OUT_R */ + outl(0x00, PME_IO_BASE_ADDR + 0x37); + + /* GP36 - KBRST */ + outl(0x00, PME_IO_BASE_ADDR + 0x39); + + /* GP37 - A20GATE */ + outl(0x00, PME_IO_BASE_ADDR + 0x3a); + + /* GP42 - GPIO_PME_OUT */ + outl(0x00, PME_IO_BASE_ADDR + 0x3d); + + /* GP50 - SER2_RI */ + outl(0x05, PME_IO_BASE_ADDR + 0x3f); + + /* GP51 - SER2_DCD */ + outl(0x05, PME_IO_BASE_ADDR + 0x40); + + /* GP52 - SER2_RX */ + outl(0x05, PME_IO_BASE_ADDR + 0x41); + + /* GP53 - SER2_TX */ + outl(0x04, PME_IO_BASE_ADDR + 0x42); + + /* GP55 - SER2_RTS */ + outl(0x04, PME_IO_BASE_ADDR + 0x44); + + /* GP56 - SER2_CTS */ + outl(0x05, PME_IO_BASE_ADDR + 0x45); + + /* GP57 - SER2_DTR */ + outl(0x04, PME_IO_BASE_ADDR + 0x46); + + /* GP60 - LED_GREEN */ + outl(0x01, PME_IO_BASE_ADDR + 0x47); + + /* GP61 - LED_YELLOW */ + outl(0x01, PME_IO_BASE_ADDR + 0x48); + + /* GP3 */ + outl(0xc0, PME_IO_BASE_ADDR + 0x4d); + + /* GP4 */ + outl(0x04, PME_IO_BASE_ADDR + 0x4e); + + /* FAN1 */ + outl(0x01, PME_IO_BASE_ADDR + 0x56); + + /* FAN2 */ + outl(0x01, PME_IO_BASE_ADDR + 0x57); + + /* Fan Control */ + outl(0x50, PME_IO_BASE_ADDR + 0x58); + + /* Fan1 Tachometer */ + outl(0xff, PME_IO_BASE_ADDR + 0x59); + + /* Fan2 Tachometer */ + outl(0xff, PME_IO_BASE_ADDR + 0x5a); + + /* LED1 */ + outl(0x00, PME_IO_BASE_ADDR + 0x5d); + + /* LED2 */ + outl(0x00, PME_IO_BASE_ADDR + 0x5e); + + /* Keyboard Scan Code */ + outl(0x00, PME_IO_BASE_ADDR + 0x5f); + + /* Exit the configuration state. */ + outb(0xaa, port); +} -- cgit v1.2.3