From 88766be48806a10d870e7a3e3fddbf7e6998056c Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Thu, 22 Dec 2016 13:53:16 +0530 Subject: mainboard/google/chell: Set TCC activation offset to 10 degree C With the default TCC activation offset value as 0 and Tjmax temperature value as 100 degree C, Pcode firmware starts taking prochot action at 100 degree C [Tjmax-Offset]. But before Pcode firmware starts prochot action at 100 degree C, device is getting shutdown at 99 degree C due to DPTF critical CPU temperature. This patch sets TCC activation offset value to 10 degree C for thermal throttle action to prevent this kind of shutdown. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built, booted on skylake and verified target offset value. Change-Id: I0811ef481a4b3ce4bd6ef24f2aa8160f44f9c990 Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/17921 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/chell/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 34250d3450..2ffaec6946 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -183,6 +183,8 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" + register "tcc_offset" = "10" # TCC of 90C + # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" -- cgit v1.2.3