From 84fdda381224f0371e27ef3f0ad77ee1103cb05a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 10 Apr 2018 15:18:38 +0200 Subject: nb/intel/pineview: Use parallel MP init Remove guards around CPU code on which all platforms use parallel MP init code. This removes the option to disable HT siblings. Tested on Foxconn D41S. Change-Id: I89f7d514d75fe933c3a8858da37004419189674b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/25602 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/foxconn/d41s/cmos.layout | 1 - src/mainboard/intel/d510mo/cmos.layout | 1 - 2 files changed, 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout index 9b9a084fc0..b006973cc3 100644 --- a/src/mainboard/foxconn/d41s/cmos.layout +++ b/src/mainboard/foxconn/d41s/cmos.layout @@ -44,7 +44,6 @@ entries 416 512 s 0 boot_devices # coreboot config options: cpu -944 1 e 2 hyper_threading #945 7 r 0 unused # coreboot config options: northbridge diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout index 9b9a084fc0..b006973cc3 100644 --- a/src/mainboard/intel/d510mo/cmos.layout +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -44,7 +44,6 @@ entries 416 512 s 0 boot_devices # coreboot config options: cpu -944 1 e 2 hyper_threading #945 7 r 0 unused # coreboot config options: northbridge -- cgit v1.2.3