From 82d7609ea942d4a8a196182f5a3c959b8c123052 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 24 May 2018 00:04:22 +0300 Subject: Remove all VIA CN700 boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I06840476ad187cbb6e6af554b5c8e8c4d66f6624 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26674 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/bcom/Kconfig | 30 -------- src/mainboard/bcom/Kconfig.name | 2 - src/mainboard/bcom/winnetp680/Kconfig | 25 ------- src/mainboard/bcom/winnetp680/Kconfig.name | 2 - src/mainboard/bcom/winnetp680/board_info.txt | 1 - src/mainboard/bcom/winnetp680/cmos.layout | 28 -------- src/mainboard/bcom/winnetp680/devicetree.cb | 64 ----------------- src/mainboard/bcom/winnetp680/irq_tables.c | 50 -------------- src/mainboard/bcom/winnetp680/romstage.c | 94 ------------------------- src/mainboard/jetway/j7f2/Kconfig | 27 -------- src/mainboard/jetway/j7f2/Kconfig.name | 2 - src/mainboard/jetway/j7f2/board_info.txt | 3 - src/mainboard/jetway/j7f2/cmos.layout | 28 -------- src/mainboard/jetway/j7f2/devicetree.cb | 62 ----------------- src/mainboard/jetway/j7f2/irq_tables.c | 50 -------------- src/mainboard/jetway/j7f2/romstage.c | 98 --------------------------- src/mainboard/jetway/j7f4k1g2e/Kconfig | 8 --- src/mainboard/jetway/j7f4k1g2e/Kconfig.name | 2 - src/mainboard/jetway/j7f4k1g2e/board_info.txt | 4 -- src/mainboard/jetway/j7f4k1g5d/Kconfig | 8 --- src/mainboard/jetway/j7f4k1g5d/Kconfig.name | 2 - src/mainboard/jetway/j7f4k1g5d/board_info.txt | 4 -- src/mainboard/via/epia-cn/Kconfig | 25 ------- src/mainboard/via/epia-cn/Kconfig.name | 2 - src/mainboard/via/epia-cn/board_info.txt | 4 -- src/mainboard/via/epia-cn/cmos.layout | 28 -------- src/mainboard/via/epia-cn/devicetree.cb | 61 ----------------- src/mainboard/via/epia-cn/irq_tables.c | 49 -------------- src/mainboard/via/epia-cn/romstage.c | 86 ----------------------- src/mainboard/via/pc2500e/Kconfig | 35 ---------- src/mainboard/via/pc2500e/Kconfig.name | 2 - src/mainboard/via/pc2500e/board_info.txt | 6 -- src/mainboard/via/pc2500e/cmos.layout | 43 ------------ src/mainboard/via/pc2500e/devicetree.cb | 89 ------------------------ src/mainboard/via/pc2500e/irq_tables.c | 49 -------------- src/mainboard/via/pc2500e/mptable.c | 95 -------------------------- src/mainboard/via/pc2500e/romstage.c | 61 ----------------- src/mainboard/winnet/Kconfig | 32 --------- src/mainboard/winnet/Kconfig.name | 4 -- src/mainboard/winnet/g170/Kconfig | 47 ------------- src/mainboard/winnet/g170/Kconfig.name | 5 -- src/mainboard/winnet/g170/acpi_tables.c | 51 -------------- src/mainboard/winnet/g170/board_info.txt | 9 --- src/mainboard/winnet/g170/cmos.layout | 28 -------- src/mainboard/winnet/g170/config_seabios | 3 - src/mainboard/winnet/g170/devicetree.cb | 64 ----------------- src/mainboard/winnet/g170/dsdt.asl | 43 ------------ src/mainboard/winnet/g170/irq_tables.c | 50 -------------- src/mainboard/winnet/g170/mainboard.c | 55 --------------- src/mainboard/winnet/g170/romstage.c | 94 ------------------------- 50 files changed, 1714 deletions(-) delete mode 100644 src/mainboard/bcom/Kconfig delete mode 100644 src/mainboard/bcom/Kconfig.name delete mode 100644 src/mainboard/bcom/winnetp680/Kconfig delete mode 100644 src/mainboard/bcom/winnetp680/Kconfig.name delete mode 100644 src/mainboard/bcom/winnetp680/board_info.txt delete mode 100644 src/mainboard/bcom/winnetp680/cmos.layout delete mode 100644 src/mainboard/bcom/winnetp680/devicetree.cb delete mode 100644 src/mainboard/bcom/winnetp680/irq_tables.c delete mode 100644 src/mainboard/bcom/winnetp680/romstage.c delete mode 100644 src/mainboard/jetway/j7f2/Kconfig delete mode 100644 src/mainboard/jetway/j7f2/Kconfig.name delete mode 100644 src/mainboard/jetway/j7f2/board_info.txt delete mode 100644 src/mainboard/jetway/j7f2/cmos.layout delete mode 100644 src/mainboard/jetway/j7f2/devicetree.cb delete mode 100644 src/mainboard/jetway/j7f2/irq_tables.c delete mode 100644 src/mainboard/jetway/j7f2/romstage.c delete mode 100644 src/mainboard/jetway/j7f4k1g2e/Kconfig delete mode 100644 src/mainboard/jetway/j7f4k1g2e/Kconfig.name delete mode 100644 src/mainboard/jetway/j7f4k1g2e/board_info.txt delete mode 100644 src/mainboard/jetway/j7f4k1g5d/Kconfig delete mode 100644 src/mainboard/jetway/j7f4k1g5d/Kconfig.name delete mode 100644 src/mainboard/jetway/j7f4k1g5d/board_info.txt delete mode 100644 src/mainboard/via/epia-cn/Kconfig delete mode 100644 src/mainboard/via/epia-cn/Kconfig.name delete mode 100644 src/mainboard/via/epia-cn/board_info.txt delete mode 100644 src/mainboard/via/epia-cn/cmos.layout delete mode 100644 src/mainboard/via/epia-cn/devicetree.cb delete mode 100644 src/mainboard/via/epia-cn/irq_tables.c delete mode 100644 src/mainboard/via/epia-cn/romstage.c delete mode 100644 src/mainboard/via/pc2500e/Kconfig delete mode 100644 src/mainboard/via/pc2500e/Kconfig.name delete mode 100644 src/mainboard/via/pc2500e/board_info.txt delete mode 100644 src/mainboard/via/pc2500e/cmos.layout delete mode 100644 src/mainboard/via/pc2500e/devicetree.cb delete mode 100644 src/mainboard/via/pc2500e/irq_tables.c delete mode 100644 src/mainboard/via/pc2500e/mptable.c delete mode 100644 src/mainboard/via/pc2500e/romstage.c delete mode 100644 src/mainboard/winnet/Kconfig delete mode 100644 src/mainboard/winnet/Kconfig.name delete mode 100644 src/mainboard/winnet/g170/Kconfig delete mode 100644 src/mainboard/winnet/g170/Kconfig.name delete mode 100644 src/mainboard/winnet/g170/acpi_tables.c delete mode 100644 src/mainboard/winnet/g170/board_info.txt delete mode 100644 src/mainboard/winnet/g170/cmos.layout delete mode 100644 src/mainboard/winnet/g170/config_seabios delete mode 100644 src/mainboard/winnet/g170/devicetree.cb delete mode 100644 src/mainboard/winnet/g170/dsdt.asl delete mode 100644 src/mainboard/winnet/g170/irq_tables.c delete mode 100644 src/mainboard/winnet/g170/mainboard.c delete mode 100644 src/mainboard/winnet/g170/romstage.c (limited to 'src/mainboard') diff --git a/src/mainboard/bcom/Kconfig b/src/mainboard/bcom/Kconfig deleted file mode 100644 index 2dfa577075..0000000000 --- a/src/mainboard/bcom/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_BCOM - -choice - prompt "Mainboard model" - -source "src/mainboard/bcom/*/Kconfig.name" - -endchoice - -source "src/mainboard/bcom/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "BCOM" - -endif # VENDOR_BCOM diff --git a/src/mainboard/bcom/Kconfig.name b/src/mainboard/bcom/Kconfig.name deleted file mode 100644 index ac9686b47d..0000000000 --- a/src/mainboard/bcom/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_BCOM - bool "BCOM" diff --git a/src/mainboard/bcom/winnetp680/Kconfig b/src/mainboard/bcom/winnetp680/Kconfig deleted file mode 100644 index c328c3fa79..0000000000 --- a/src/mainboard/bcom/winnetp680/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if BOARD_BCOM_WINNETP680 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_VIA_C7 - select NORTHBRIDGE_VIA_CN700 - select SOUTHBRIDGE_VIA_VT8237R - select SUPERIO_WINBOND_W83697HF - select HAVE_PIRQ_TABLE - select HAVE_OPTION_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default bcom/winnetp680 - -config MAINBOARD_PART_NUMBER - string - default "WinNET P680" - -config IRQ_SLOT_COUNT - int - default 10 - -endif # BOARD_BCOM_WINNETP680 diff --git a/src/mainboard/bcom/winnetp680/Kconfig.name b/src/mainboard/bcom/winnetp680/Kconfig.name deleted file mode 100644 index 5b09e7a366..0000000000 --- a/src/mainboard/bcom/winnetp680/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_BCOM_WINNETP680 - bool "WinNET P680" diff --git a/src/mainboard/bcom/winnetp680/board_info.txt b/src/mainboard/bcom/winnetp680/board_info.txt deleted file mode 100644 index 0ba2657f1a..0000000000 --- a/src/mainboard/bcom/winnetp680/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: settop diff --git a/src/mainboard/bcom/winnetp680/cmos.layout b/src/mainboard/bcom/winnetp680/cmos.layout deleted file mode 100644 index b238a379d8..0000000000 --- a/src/mainboard/bcom/winnetp680/cmos.layout +++ /dev/null @@ -1,28 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -456 1 e 1 ECC_memory -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/bcom/winnetp680/devicetree.cb b/src/mainboard/bcom/winnetp680/devicetree.cb deleted file mode 100644 index f0a086b642..0000000000 --- a/src/mainboard/bcom/winnetp680/devicetree.cb +++ /dev/null @@ -1,64 +0,0 @@ -chip northbridge/via/cn700 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci f.0 on end # IDE - device pci 10.0 on end # UHCI - device pci 10.1 on end # UHCI - device pci 10.2 on end # UHCI - device pci 10.3 on end # UHCI - device pci 10.4 on end # EHCI - device pci 11.0 on # Southbridge LPC - chip superio/winbond/w83697hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 off end # Consumer IR - device pnp 2e.7 off end # Game port, GPIO 1 - device pnp 2e.8 off end # MIDI port, GPIO 5 - device pnp 2e.9 off end # GPIO 2-4 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HWM - io 0x60 = 0x290 - end - end - end - device pci 11.5 on end # AC'97 audio - device pci 12.0 on end # Ethernet - end - end - device cpu_cluster 0 on # APIC cluster - chip cpu/via/c7 # VIA C7 - device lapic 0 on end # APIC - end - end -end diff --git a/src/mainboard/bcom/winnetp680/irq_tables.c b/src/mainboard/bcom/winnetp680/irq_tables.c deleted file mode 100644 index 15263cc817..0000000000 --- a/src/mainboard/bcom/winnetp680/irq_tables.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Aaron Lwe for VIA) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0x828, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x3e, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, - {0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c deleted file mode 100644 index 0703ba6348..0000000000 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Aaron Lwe for VIA) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) - -int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -static void enable_mainboard_devices(void) -{ - pci_devfn_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev == PCI_DEV_INVALID) - die("Southbridge not found!!!\n"); - - /* bit = 0 means enable function (per CX700 datasheet) - * 5 16.1 USB 2 - * 4 16.0 USB 1 - * 3 15.0 SATA and PATA - * 2 16.2 USB 3 - * 1 16.4 USB EHCI - */ - pci_write_config8(dev, 0x50, 0x80); - - /* bit = 1 means enable internal function (per CX700 datasheet) - * 3 Internal RTC - * 2 Internal PS2 Mouse - * 1 Internal KBC Configuration - * 0 Internal Keyboard Controller - */ - pci_write_config8(dev, 0x51, 0x1d); -} - -static const struct mem_controller ctrl = { - .d0f0 = 0x0000, - .d0f2 = 0x2000, - .d0f3 = 0x3000, - .d0f4 = 0x4000, - .d0f7 = 0x7000, - .d1f0 = 0x8000, - .channel0 = { DIMM0 }, -}; - -void main(unsigned long bist) -{ - /* Enable multifunction for northbridge. */ - pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - - winbond_set_clksel_48(SERIAL_DEV); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0)); - - /* Halt if there was a built-in self test failure. */ - report_bist_failure(bist); - - enable_mainboard_devices(); - - ddr_ram_setup(&ctrl); -} diff --git a/src/mainboard/jetway/j7f2/Kconfig b/src/mainboard/jetway/j7f2/Kconfig deleted file mode 100644 index 48a85a14a4..0000000000 --- a/src/mainboard/jetway/j7f2/Kconfig +++ /dev/null @@ -1,27 +0,0 @@ -if BOARD_JETWAY_J7F2 || BOARD_JETWAY_J7F4K1G2E || BOARD_JETWAY_J7F4K1G5D - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_VIA_C7 - select NORTHBRIDGE_VIA_CN700 - select SOUTHBRIDGE_VIA_VT8237R - select SUPERIO_FINTEK_F71805F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default jetway/j7f2 - -if BOARD_JETWAY_J7F2 -config MAINBOARD_PART_NUMBER - string - default "J7f2" -endif # BOARD_JETWAY_J7F2 - -config IRQ_SLOT_COUNT - int - default 10 - -endif # BOARD_JETWAY_J7F2 || BOARD_JETWAY_J7F4K1G2E || BOARD_JETWAY_J7F4K1G5D diff --git a/src/mainboard/jetway/j7f2/Kconfig.name b/src/mainboard/jetway/j7f2/Kconfig.name deleted file mode 100644 index 0261d1642b..0000000000 --- a/src/mainboard/jetway/j7f2/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_JETWAY_J7F2 - bool "J7F2" diff --git a/src/mainboard/jetway/j7f2/board_info.txt b/src/mainboard/jetway/j7f2/board_info.txt deleted file mode 100644 index 709f95ce6d..0000000000 --- a/src/mainboard/jetway/j7f2/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F2 -Category: mini -Release year: 2008 diff --git a/src/mainboard/jetway/j7f2/cmos.layout b/src/mainboard/jetway/j7f2/cmos.layout deleted file mode 100644 index b238a379d8..0000000000 --- a/src/mainboard/jetway/j7f2/cmos.layout +++ /dev/null @@ -1,28 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -456 1 e 1 ECC_memory -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/jetway/j7f2/devicetree.cb b/src/mainboard/jetway/j7f2/devicetree.cb deleted file mode 100644 index ce5589f316..0000000000 --- a/src/mainboard/jetway/j7f2/devicetree.cb +++ /dev/null @@ -1,62 +0,0 @@ -chip northbridge/via/cn700 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci a.0 on end # Firewire - device pci f.0 on end # SATA - device pci f.1 on end # IDE - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI - device pci 10.4 on end # EHCI - device pci 11.0 on # Southbridge LPC - chip superio/fintek/f71805f # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - end - end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 Modem - device pci 12.0 on end # Ethernet - end - end - device cpu_cluster 0 on # APIC cluster - chip cpu/via/c7 # VIA C7 - device lapic 0 on end # APIC - end - end -end diff --git a/src/mainboard/jetway/j7f2/irq_tables.c b/src/mainboard/jetway/j7f2/irq_tables.c deleted file mode 100644 index 15263cc817..0000000000 --- a/src/mainboard/jetway/j7f2/irq_tables.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Aaron Lwe for VIA) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0x828, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x3e, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, - {0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c deleted file mode 100644 index 186c768168..0000000000 --- a/src/mainboard/jetway/j7f2/romstage.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Aaron Lwe for VIA) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if CONFIG_TTYS0_BASE == 0x2f8 -#define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2) -#else -#define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1) -#endif - -int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -static void enable_mainboard_devices(void) -{ - pci_devfn_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev == PCI_DEV_INVALID) - die("Southbridge not found!!!\n"); - - /* bit=0 means enable function (per CX700 datasheet) - * 5 16.1 USB 2 - * 4 16.0 USB 1 - * 3 15.0 SATA and PATA - * 2 16.2 USB 3 - * 1 16.4 USB EHCI - */ - pci_write_config8(dev, 0x50, 0x80); - - /* bit=1 means enable internal function (per CX700 datasheet) - * 3 Internal RTC - * 2 Internal PS2 Mouse - * 1 Internal KBC Configuration - * 0 Internal Keyboard Controller - */ - pci_write_config8(dev, 0x51, 0x1d); -} - -static const struct mem_controller ctrl = { - .d0f0 = 0x0000, - .d0f2 = 0x2000, - .d0f3 = 0x3000, - .d0f4 = 0x4000, - .d0f7 = 0x7000, - .d1f0 = 0x8000, - .channel0 = { DIMM0 }, -}; - -void main(unsigned long bist) -{ - /* Enable multifunction for northbridge. */ - pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0)); - - /* Halt if there was a built-in self test failure. */ - report_bist_failure(bist); - - enable_mainboard_devices(); - - ddr_ram_setup(&ctrl); -} diff --git a/src/mainboard/jetway/j7f4k1g2e/Kconfig b/src/mainboard/jetway/j7f4k1g2e/Kconfig deleted file mode 100644 index 8c8bbaf361..0000000000 --- a/src/mainboard/jetway/j7f4k1g2e/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -if BOARD_JETWAY_J7F4K1G2E - -# Dummy for abuild - -config MAINBOARD_PART_NUMBER - string - default "J7f4K1G2E" -endif diff --git a/src/mainboard/jetway/j7f4k1g2e/Kconfig.name b/src/mainboard/jetway/j7f4k1g2e/Kconfig.name deleted file mode 100644 index 67c6379f27..0000000000 --- a/src/mainboard/jetway/j7f4k1g2e/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_JETWAY_J7F4K1G2E - bool "J7F4K1G2E" diff --git a/src/mainboard/jetway/j7f4k1g2e/board_info.txt b/src/mainboard/jetway/j7f4k1g2e/board_info.txt deleted file mode 100644 index 42f29ecb5c..0000000000 --- a/src/mainboard/jetway/j7f4k1g2e/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G2E -Category: mini -Clone of: jetway/j7f2 -Release year: 2009 diff --git a/src/mainboard/jetway/j7f4k1g5d/Kconfig b/src/mainboard/jetway/j7f4k1g5d/Kconfig deleted file mode 100644 index d59e703d6c..0000000000 --- a/src/mainboard/jetway/j7f4k1g5d/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -if BOARD_JETWAY_J7F4K1G5D - -# Dummy for abuild - -config MAINBOARD_PART_NUMBER - string - default "J7f4K1G5D" -endif diff --git a/src/mainboard/jetway/j7f4k1g5d/Kconfig.name b/src/mainboard/jetway/j7f4k1g5d/Kconfig.name deleted file mode 100644 index 56fbd1e6fe..0000000000 --- a/src/mainboard/jetway/j7f4k1g5d/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_JETWAY_J7F4K1G5D - bool "J7F4K1G5D" diff --git a/src/mainboard/jetway/j7f4k1g5d/board_info.txt b/src/mainboard/jetway/j7f4k1g5d/board_info.txt deleted file mode 100644 index f489257956..0000000000 --- a/src/mainboard/jetway/j7f4k1g5d/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G5D -Category: mini -Clone of: jetway/j7f2 -Release year: 2008 diff --git a/src/mainboard/via/epia-cn/Kconfig b/src/mainboard/via/epia-cn/Kconfig deleted file mode 100644 index 266e7e9d1f..0000000000 --- a/src/mainboard/via/epia-cn/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if BOARD_VIA_EPIA_CN - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_VIA_C7 - select NORTHBRIDGE_VIA_CN700 - select SOUTHBRIDGE_VIA_VT8237R - select SUPERIO_VIA_VT1211 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default via/epia-cn - -config MAINBOARD_PART_NUMBER - string - default "EPIA-CN" - -config IRQ_SLOT_COUNT - int - default 9 - -endif # BOARD_VIA_EPIA_CN diff --git a/src/mainboard/via/epia-cn/Kconfig.name b/src/mainboard/via/epia-cn/Kconfig.name deleted file mode 100644 index 1664fe29de..0000000000 --- a/src/mainboard/via/epia-cn/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_VIA_EPIA_CN - bool "EPIA-CN" diff --git a/src/mainboard/via/epia-cn/board_info.txt b/src/mainboard/via/epia-cn/board_info.txt deleted file mode 100644 index f3fe3a3360..0000000000 --- a/src/mainboard/via/epia-cn/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: mini -Board name: EPIA-CN10000EG / EPIA-CN13000G -Board URL: http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 -Release year: 2006 diff --git a/src/mainboard/via/epia-cn/cmos.layout b/src/mainboard/via/epia-cn/cmos.layout deleted file mode 100644 index b238a379d8..0000000000 --- a/src/mainboard/via/epia-cn/cmos.layout +++ /dev/null @@ -1,28 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -456 1 e 1 ECC_memory -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/via/epia-cn/devicetree.cb b/src/mainboard/via/epia-cn/devicetree.cb deleted file mode 100644 index 028cb884af..0000000000 --- a/src/mainboard/via/epia-cn/devicetree.cb +++ /dev/null @@ -1,61 +0,0 @@ -chip northbridge/via/cn700 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - device pci f.0 on end # IDE - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI - device pci 10.4 on end # EHCI - device pci 10.5 on end # UDCI - device pci 11.0 on # Southbridge LPC - chip superio/via/vt1211 # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - end - end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 Modem - device pci 12.0 on end # Ethernet - end - end - device cpu_cluster 0 on # APIC cluster - chip cpu/via/c7 # VIA C7 - device lapic 0 on end # APIC - end - end -end diff --git a/src/mainboard/via/epia-cn/irq_tables.c b/src/mainboard/via/epia-cn/irq_tables.c deleted file mode 100644 index ee8d488f97..0000000000 --- a/src/mainboard/via/epia-cn/irq_tables.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Aaron Lwe for VIA) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0xc20, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x66, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x14 << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0d << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0e << 3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x13 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x11 << 3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x0f << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x10 << 3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x12 << 3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c deleted file mode 100644 index 6ac652e777..0000000000 --- a/src/mainboard/via/epia-cn/romstage.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Aaron Lwe for VIA) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "southbridge/via/vt8237r/early_serial.c" -#include - -int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -static void enable_mainboard_devices(void) -{ - pci_devfn_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev == PCI_DEV_INVALID) - die("Southbridge not found!!!\n"); - - /* bit = 0 means enable function (per CX700 datasheet) - * 5 16.1 USB 2 - * 4 16.0 USB 1 - * 3 15.0 SATA and PATA - * 2 16.2 USB 3 - * 1 16.4 USB EHCI - */ - pci_write_config8(dev, 0x50, 0x80); - - /* bit = 1 means enable internal function (per CX700 datasheet) - * 3 Internal RTC - * 2 Internal PS2 Mouse - * 1 Internal KBC Configuration - * 0 Internal Keyboard Controller - */ - pci_write_config8(dev, 0x51, 0x1d); -} - -static const struct mem_controller ctrl = { - .d0f0 = 0x0000, - .d0f2 = 0x2000, - .d0f3 = 0x3000, - .d0f4 = 0x4000, - .d0f7 = 0x7000, - .d1f0 = 0x8000, - .channel0 = { DIMM0 }, -}; - -void main(unsigned long bist) -{ - /* Enable multifunction for northbridge. */ - pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - - enable_vt8237r_serial(); - console_init(); - enable_smbus(); - smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0)); - report_bist_failure(bist); - enable_mainboard_devices(); - ddr_ram_setup(&ctrl); -} diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig deleted file mode 100644 index d5e1133a64..0000000000 --- a/src/mainboard/via/pc2500e/Kconfig +++ /dev/null @@ -1,35 +0,0 @@ -if BOARD_VIA_PC2500E - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_VIA_C7 - select NORTHBRIDGE_VIA_CN700 - select SOUTHBRIDGE_VIA_VT8237R - select SUPERIO_ITE_IT8716F - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SMP - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default via/pc2500e - -config MAINBOARD_PART_NUMBER - string - default "pc2500e" - -config IRQ_SLOT_COUNT - int - default 10 - -config VGA_BIOS_FILE - string - default "M14CRT.ROM" - -config VGA_BIOS_ID - string - default "1106,3344" - -endif # BOARD_VIA_PC2500E diff --git a/src/mainboard/via/pc2500e/Kconfig.name b/src/mainboard/via/pc2500e/Kconfig.name deleted file mode 100644 index 0de65a7e7e..0000000000 --- a/src/mainboard/via/pc2500e/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_VIA_PC2500E - bool "pc2500e" diff --git a/src/mainboard/via/pc2500e/board_info.txt b/src/mainboard/via/pc2500e/board_info.txt deleted file mode 100644 index 8b98abf4d2..0000000000 --- a/src/mainboard/via/pc2500e/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: mini -Board URL: http://www.idot.com.tw/en/products/mb-pc2500e/ -ROM package: PLCC -ROM socketed: y -Flashrom support: y -Release year: 2007 diff --git a/src/mainboard/via/pc2500e/cmos.layout b/src/mainboard/via/pc2500e/cmos.layout deleted file mode 100644 index 6d8fd5b05a..0000000000 --- a/src/mainboard/via/pc2500e/cmos.layout +++ /dev/null @@ -1,43 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -entries - -#start-bit length config config-ID name -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -456 1 e 1 ECC_memory -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/via/pc2500e/devicetree.cb b/src/mainboard/via/pc2500e/devicetree.cb deleted file mode 100644 index 17bc35efc9..0000000000 --- a/src/mainboard/via/pc2500e/devicetree.cb +++ /dev/null @@ -1,89 +0,0 @@ -chip northbridge/via/cn700 # Northbridge - device domain 0 on # PCI domain - subsystemid 0x1019 0xaa51 inherit - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - device pci f.0 on end # SATA - device pci f.1 on end # IDE - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci 10.0 on end # UHCI - device pci 10.1 on end # UHCI - device pci 10.2 on end # UHCI - device pci 10.3 on end # UHCI - device pci 10.4 on end # EHCI - device pci 10.5 on end # UDCI - device pci 11.0 on # Southbridge LPC - chip superio/ite/it8716f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # COM2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x0000 - irq 0x70 = 9 - end - device pnp 2e.5 off # PS/2 keyboard (not used) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # PS/2 mouse (not used) - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x0000 - io 0x62 = 0x0800 - io 0x64 = 0x0000 - end - device pnp 2e.8 off # MIDI port (N/A) - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # Game port (N/A) - io 0x60 = 0x201 - end - device pnp 2e.a on # Consumer IR - io 0x60 = 0x310 - irq 0x70 = 11 - end - end - end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 modem (N/A) - device pci 12.0 on end # Ethernet - end - end - device cpu_cluster 0 on # APIC cluster - chip cpu/via/c7 # VIA C7 - device lapic 0 on end # APIC - end - end -end diff --git a/src/mainboard/via/pc2500e/irq_tables.c b/src/mainboard/via/pc2500e/irq_tables.c deleted file mode 100644 index e514df4363..0000000000 --- a/src/mainboard/via/pc2500e/irq_tables.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0x828, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x3e, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, - {0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c deleted file mode 100644 index 9b92b002cf..0000000000 --- a/src/mainboard/via/pc2500e/mptable.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu for AMD) - * Copyright (C) 2007 Philipp Degler - * (Thanks to LSRA University of Mannheim for their support) - * Copyright (C) 2008 Jonathan A. Kollasch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "southbridge/via/vt8237r/vt8237r.h" - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - mptable_write_buses(mc, NULL, &isa_bus); - -/* I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR); - - /* Now, assemble the table. */ - mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0); - -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \ - bus, (((dev)<<2)|(fn)), VT8237R_APIC_ID, (pin)) - - // PCI slot 1 - PCI_INT(0, 8, 0, 16); - PCI_INT(0, 8, 1, 17); - PCI_INT(0, 8, 2, 18); - PCI_INT(0, 8, 3, 19); - - // PCI slot 2 - PCI_INT(0, 9, 0, 17); - PCI_INT(0, 9, 1, 18); - PCI_INT(0, 9, 2, 19); - PCI_INT(0, 9, 3, 16); - - // SATA - PCI_INT(0, 15, 1, 20); - - // USB - PCI_INT(0, 16, 0, 21); - PCI_INT(0, 16, 1, 21); - PCI_INT(0, 16, 2, 21); - PCI_INT(0, 16, 3, 21); - - // Audio - PCI_INT(0, 17, 2, 22); - - // Ethernet - PCI_INT(0, 18, 0, 23); - - /* Onboard VGA */ - PCI_INT(1, 0, 0, 16); - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, 0); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c deleted file mode 100644 index d0ecae361d..0000000000 --- a/src/mainboard/via/pc2500e/romstage.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) - -int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -static const struct mem_controller ctrl = { - .d0f0 = 0x0000, - .d0f2 = 0x2000, - .d0f3 = 0x3000, - .d0f4 = 0x4000, - .d0f7 = 0x7000, - .d1f0 = 0x8000, - .channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */ -}; - -void main(unsigned long bist) -{ - /* Enable multifunction for northbridge. */ - pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); - smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0)); - report_bist_failure(bist); - ddr_ram_setup(&ctrl); -} diff --git a/src/mainboard/winnet/Kconfig b/src/mainboard/winnet/Kconfig deleted file mode 100644 index d9c3e9c3d2..0000000000 --- a/src/mainboard/winnet/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2017 Lubomir Rintel -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if VENDOR_WINNET - -choice - prompt "Mainboard model" - -source "src/mainboard/winnet/*/Kconfig.name" - -endchoice - -source "src/mainboard/winnet/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "WinNET" - -endif # VENDOR_WINNET diff --git a/src/mainboard/winnet/Kconfig.name b/src/mainboard/winnet/Kconfig.name deleted file mode 100644 index ebd4a38ec7..0000000000 --- a/src/mainboard/winnet/Kconfig.name +++ /dev/null @@ -1,4 +0,0 @@ -config VENDOR_WINNET - bool "WinNET" - help - WinNET boards. Used in various thin client appliances. diff --git a/src/mainboard/winnet/g170/Kconfig b/src/mainboard/winnet/g170/Kconfig deleted file mode 100644 index d4827529bc..0000000000 --- a/src/mainboard/winnet/g170/Kconfig +++ /dev/null @@ -1,47 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2017 Lubomir Rintel -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_WINNET_G170 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_VIA_C7 - select NORTHBRIDGE_VIA_CN700 - select SOUTHBRIDGE_VIA_VT8237R - select SUPERIO_WINBOND_W83697HF - select HAVE_PIRQ_TABLE - select HAVE_OPTION_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default winnet/g170 - -config MAINBOARD_PART_NUMBER - string - default "G170" - -config IRQ_SLOT_COUNT - int - default 10 - -config PAYLOAD_CONFIGFILE - string - depends on PAYLOAD_SEABIOS - default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" - -endif # BOARD_WINNET_G170 diff --git a/src/mainboard/winnet/g170/Kconfig.name b/src/mainboard/winnet/g170/Kconfig.name deleted file mode 100644 index e0e0d222a6..0000000000 --- a/src/mainboard/winnet/g170/Kconfig.name +++ /dev/null @@ -1,5 +0,0 @@ -config BOARD_WINNET_G170 - bool "WinNET G170 (Neoware CA19, IGEL 2110)" - help - G170 is a board manufactured by WinNET, used in thin clients including - HP Neoware CA19 and IGEL 2110. diff --git a/src/mainboard/winnet/g170/acpi_tables.c b/src/mainboard/winnet/g170/acpi_tables.c deleted file mode 100644 index 129dc25129..0000000000 --- a/src/mainboard/winnet/g170/acpi_tables.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Based on mainboard/via/epia-m700/acpi_tables.c - * - * Copyright (C) 2004 Stefan Reinauer - * Copyright (C) 2005 Nick Barker - * Copyright (C) 2007 Rudolf Marek - * Copyright (C) 2017 Lubomir Rintel - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "southbridge/via/vt8237r/vt8237r.h" - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Create all subtables for processors. */ - current = acpi_create_madt_lapics(current); - - /* Write SB IOAPIC. */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - VT8237R_APIC_ID, IO_APIC_ADDR, 0); - - /* IRQ9 ACPI active low. */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); - - /* IRQ0 -> APIC IRQ2. */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); - - return current; -} diff --git a/src/mainboard/winnet/g170/board_info.txt b/src/mainboard/winnet/g170/board_info.txt deleted file mode 100644 index c3364601b1..0000000000 --- a/src/mainboard/winnet/g170/board_info.txt +++ /dev/null @@ -1,9 +0,0 @@ -Category: mini -Vendor name: WinNET -Board name: G170 -ROM package: PLCC -ROM protocol: Parallel -ROM socketed: y -Flashrom support: y -Release year: 2006 -Clone of: bcom/winnetp680 diff --git a/src/mainboard/winnet/g170/cmos.layout b/src/mainboard/winnet/g170/cmos.layout deleted file mode 100644 index 9ab6f785b6..0000000000 --- a/src/mainboard/winnet/g170/cmos.layout +++ /dev/null @@ -1,28 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 8 e unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -456 1 e 1 ECC_memory -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/winnet/g170/config_seabios b/src/mainboard/winnet/g170/config_seabios deleted file mode 100644 index eca372da58..0000000000 --- a/src/mainboard/winnet/g170/config_seabios +++ /dev/null @@ -1,3 +0,0 @@ -# VT8237R won't DMA between 0xc0000 and 0x100000 - -# CONFIG_MALLOC_UPPERMEMORY is not set diff --git a/src/mainboard/winnet/g170/devicetree.cb b/src/mainboard/winnet/g170/devicetree.cb deleted file mode 100644 index f0a086b642..0000000000 --- a/src/mainboard/winnet/g170/devicetree.cb +++ /dev/null @@ -1,64 +0,0 @@ -chip northbridge/via/cn700 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci f.0 on end # IDE - device pci 10.0 on end # UHCI - device pci 10.1 on end # UHCI - device pci 10.2 on end # UHCI - device pci 10.3 on end # UHCI - device pci 10.4 on end # EHCI - device pci 11.0 on # Southbridge LPC - chip superio/winbond/w83697hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 off end # Consumer IR - device pnp 2e.7 off end # Game port, GPIO 1 - device pnp 2e.8 off end # MIDI port, GPIO 5 - device pnp 2e.9 off end # GPIO 2-4 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HWM - io 0x60 = 0x290 - end - end - end - device pci 11.5 on end # AC'97 audio - device pci 12.0 on end # Ethernet - end - end - device cpu_cluster 0 on # APIC cluster - chip cpu/via/c7 # VIA C7 - device lapic 0 on end # APIC - end - end -end diff --git a/src/mainboard/winnet/g170/dsdt.asl b/src/mainboard/winnet/g170/dsdt.asl deleted file mode 100644 index 17e6a3e084..0000000000 --- a/src/mainboard/winnet/g170/dsdt.asl +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Lubomir Rintel - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20170227 // OEM revision -) -{ - /* Sleep states */ - Name (\_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 }) - Name (\_S5, Package (0x04) { 0x02, 0x02, 0x02, 0x02 }) - - /* Interrupt model */ - Method (_PIC, 1) { - Store (Arg0, \_SB.PCI0.ISAC.APIC) - } - - Scope (\_SB) { - /* PCI bus */ - Device (PCI0) { - #include - #include - #include - } - } -} diff --git a/src/mainboard/winnet/g170/irq_tables.c b/src/mainboard/winnet/g170/irq_tables.c deleted file mode 100644 index 15263cc817..0000000000 --- a/src/mainboard/winnet/g170/irq_tables.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Aaron Lwe for VIA) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0x828, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x3e, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, - {0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, - {0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, - {0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, - {0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, - {0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/winnet/g170/mainboard.c b/src/mainboard/winnet/g170/mainboard.c deleted file mode 100644 index 3f7428aa31..0000000000 --- a/src/mainboard/winnet/g170/mainboard.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Lubomir Rintel - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -static void mainboard_final(void *chip_info) -{ - /* A B C D */ - static const unsigned char irq_map[4] = { 11, 5, 10, 0 }; - struct device *lpc_dev; - - printk(BIOS_INFO, "Setting up G170 IRQ routing...\n"); - - lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); - - /* Disable APIC */ - pci_write_config8(lpc_dev, 0x58, pci_read_config8(lpc_dev, 0x58) & ~0x40); - - /* Share INTE-INTH with INTA-INTD */ - pci_write_config8(lpc_dev, 0x46, 0x00); - - /* Route INTA-INTD */ - pci_write_config8(lpc_dev, 0x55, irq_map[0] << 4); - pci_write_config8(lpc_dev, 0x56, irq_map[1] << 4 | irq_map[2]); - pci_write_config8(lpc_dev, 0x57, irq_map[3]); - - /* Assign IRQ numbers to known devices for non-PnP OSes */ - pci_assign_irqs(0x00, 0x10, irq_map); - pci_assign_irqs(0x00, 0x11, irq_map); - pci_assign_irqs(0x00, 0x12, irq_map); - pci_assign_irqs(0x01, 0x00, irq_map); -} - -struct chip_operations mainboard_ops = { - CHIP_NAME("WinNET G170") - .final = mainboard_final, -}; diff --git a/src/mainboard/winnet/g170/romstage.c b/src/mainboard/winnet/g170/romstage.c deleted file mode 100644 index 0703ba6348..0000000000 --- a/src/mainboard/winnet/g170/romstage.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 VIA Technologies, Inc. - * (Written by Aaron Lwe for VIA) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) - -int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -static void enable_mainboard_devices(void) -{ - pci_devfn_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev == PCI_DEV_INVALID) - die("Southbridge not found!!!\n"); - - /* bit = 0 means enable function (per CX700 datasheet) - * 5 16.1 USB 2 - * 4 16.0 USB 1 - * 3 15.0 SATA and PATA - * 2 16.2 USB 3 - * 1 16.4 USB EHCI - */ - pci_write_config8(dev, 0x50, 0x80); - - /* bit = 1 means enable internal function (per CX700 datasheet) - * 3 Internal RTC - * 2 Internal PS2 Mouse - * 1 Internal KBC Configuration - * 0 Internal Keyboard Controller - */ - pci_write_config8(dev, 0x51, 0x1d); -} - -static const struct mem_controller ctrl = { - .d0f0 = 0x0000, - .d0f2 = 0x2000, - .d0f3 = 0x3000, - .d0f4 = 0x4000, - .d0f7 = 0x7000, - .d1f0 = 0x8000, - .channel0 = { DIMM0 }, -}; - -void main(unsigned long bist) -{ - /* Enable multifunction for northbridge. */ - pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - - winbond_set_clksel_48(SERIAL_DEV); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0)); - - /* Halt if there was a built-in self test failure. */ - report_bist_failure(bist); - - enable_mainboard_devices(); - - ddr_ram_setup(&ctrl); -} -- cgit v1.2.3