From 819d676fed535c80d68247ed938a6559ff1c7d10 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Mon, 27 Jul 2020 12:05:26 +0530 Subject: mb/google/dedede: Fix S3 wake using trackpad Configure TRACKPAD_INT_ODL pad reset config to DEEP and map PMC_GPE_DW to PMC_GPP values. TEST=System should wake from S3 via trackpad Change-Id: I58ce3720e0fdeefb2c9440bb3006897ef80211ea Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/43949 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 6 +++--- src/mainboard/google/dedede/variants/baseboard/gpio.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index e7c5656833..13666ad3e9 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -16,9 +16,9 @@ chip soc/intel/jasperlake # - GPP_D0 - WWAN_HOST_WAKE # - GPP_D3 - WLAN_PCIE_WAKE_ODL # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. - register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_C" - register "pmc_gpe0_dw2" = "GPP_D" + register "pmc_gpe0_dw0" = "PMC_GPP_B" + register "pmc_gpe0_dw1" = "PMC_GPP_C" + register "pmc_gpe0_dw2" = "PMC_GPP_D" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 9b60da11c7..d6a2d61aca 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = { /* B2 : PROCHOT_ODL */ PAD_NC(GPP_B2, NONE), /* B3 : TRACKPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, DEEP, LEVEL, INVERT), /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), /* B5 : PCIE_CLKREQ0_N */ -- cgit v1.2.3