From 8084b3856852f3fb3905e0fe4957b08518095d38 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 10:56:31 +0100 Subject: sb/intel/lynxpoint/sata: Always use AHCI mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The other two modes are not used by any mainboard, and the code seems to be copied from older southbridges. As the code looks incorrect, drop it. Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/asrock/b85m_pro4/devicetree.cb | 1 - src/mainboard/asrock/h81m-hds/devicetree.cb | 1 - src/mainboard/google/beltino/devicetree.cb | 2 -- src/mainboard/google/slippy/devicetree.cb | 2 -- src/mainboard/intel/baskingridge/devicetree.cb | 2 -- src/mainboard/lenovo/t440p/devicetree.cb | 1 - src/mainboard/supermicro/x10slm-f/devicetree.cb | 1 - 7 files changed, 10 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index d257f18bc6..024d1f0e1f 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -27,7 +27,6 @@ chip northbridge/intel/haswell chip southbridge/intel/lynxpoint register "gen1_dec" = "0x000c0291" # Super I/O HWM - register "sata_ahci" = "1" register "sata_port_map" = "0x3f" device pci 14.0 on end # xHCI controller diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 8f368961de..45119f9476 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -35,7 +35,6 @@ chip northbridge/intel/haswell end chip southbridge/intel/lynxpoint - register "sata_ahci" = "1" register "sata_port_map" = "0x33" register "gen1_dec" = "0x00000295" # Super I/O HWM diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8fdfbd79a0..176fced5ed 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -45,8 +45,6 @@ chip northbridge/intel/haswell register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_devslp_disable" = "0x1" diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 200721b8ef..a6fab83a5b 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -52,8 +52,6 @@ chip northbridge/intel/haswell register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sio_acpi_mode" = "1" diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 6345090c7a..784c926d5f 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -41,8 +41,6 @@ chip northbridge/intel/haswell register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x4000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 8c356816ab..9359bb4e5d 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -37,7 +37,6 @@ chip northbridge/intel/haswell register "gen4_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi1_routing" = "2" - register "sata_ahci" = "1" # 0(HDD), 1(M.2), 5(ODD) register "sata_port_map" = "0x23" device pci 14.0 on end # xHCI Controller diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index ffcc56d15c..6d64a90221 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -26,7 +26,6 @@ chip northbridge/intel/haswell device pci 03.0 off end # Mini-HD audio chip southbridge/intel/lynxpoint - register "sata_ahci" = "1" register "sata_port_map" = "0x3f" register "gen1_dec" = "0x00000295" # Super I/O HWM -- cgit v1.2.3