From 7efdacd748f5292bfe09f2365ace14a614960dd0 Mon Sep 17 00:00:00 2001
From: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Date: Fri, 23 Mar 2018 22:47:45 +0530
Subject: mb/google/octopus/variants/baseboard: Enable DPTF support

This patch enables DPTF support for Octopus baseboard.

BUG=None
BRANCH=None
TEST=None

Change-Id: I88a94c73ef0c9da708c0440f7edadd85488edfdb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/25342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/mainboard/google/octopus/variants/baseboard/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mainboard')

diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index aee8668a54..7072b7874f 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -46,6 +46,9 @@ chip soc/intel/apollolake
 	# Enable lpss s0ix
 	register "lpss_s0ix_enable" = "1"
 
+	# Enable DPTF
+	register "dptf_enable" = "1"
+
 	# Enable Audio Clock and Power gating
 	register "hdaudio_clk_gate_enable" = "1"
 	register "hdaudio_pwr_gate_enable" = "1"
-- 
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