From 7c5c4fdf18820623262b78c57a9a77d0f6b45282 Mon Sep 17 00:00:00 2001
From: Jon Murphy <jpmurphy@google.com>
Date: Mon, 24 Apr 2023 10:19:51 -0600
Subject: mb/google/myst: Enable S0ix

Enable s0ix on Myst.

BUG=b:277215113
TEST=builds

Change-Id: I3cabc2c3ba75f4490da18b861ef2b82ce240860d
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74279
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/myst/variants/baseboard/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/mainboard')

diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
index 7adb365088..058f873cb5 100644
--- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
@@ -83,6 +83,7 @@ chip soc/amd/phoenix
 	register "gpp_clk_config[6]" = "GPP_CLK_OFF" # WWAN_AUX_RST_L GPIO
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works
+	register "s0ix_enable" = "true"
 
 	device domain 0 on
 		device ref gpp_bridge_2_1 on end # WWAN
-- 
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