From 7bbcdc2f207aa2ed42f713aa455ff698f958ab24 Mon Sep 17 00:00:00 2001
From: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Date: Thu, 18 Mar 2021 16:39:49 +0800
Subject: mb/google/mancomb: Add ACPI support for Chrome EC

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ibce15d2e4340515353a33c593d065df50a15286a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
---
 src/mainboard/google/mancomb/dsdt.asl                         | 11 +++++++++++
 src/mainboard/google/mancomb/variants/baseboard/devicetree.cb |  5 +++++
 2 files changed, 16 insertions(+)

(limited to 'src/mainboard')

diff --git a/src/mainboard/google/mancomb/dsdt.asl b/src/mainboard/google/mancomb/dsdt.asl
index 7b8982a645..73a2ea5da1 100644
--- a/src/mainboard/google/mancomb/dsdt.asl
+++ b/src/mainboard/google/mancomb/dsdt.asl
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
+#include <variant/ec.h>
+
 DefinitionBlock (
 	"dsdt.aml",
 	"DSDT",
@@ -13,4 +15,13 @@ DefinitionBlock (
 	#include <acpi/dsdt_top.asl>
 
 	#include <soc.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
 }
diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
index db21dd4e26..c4ef3f546b 100644
--- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
@@ -42,5 +42,10 @@ chip soc/amd/cezanne
 		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			device ref gfx on end # Internal GPU (GFX)
 		end
+		device ref lpc_bridge on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
 	end # domain
 end	# chip soc/amd/cezanne
-- 
cgit v1.2.3