From 7ac6a987d03c3dc9e39c27fda76a2e8642376817 Mon Sep 17 00:00:00 2001 From: Anil Kumar Date: Wed, 13 May 2020 13:07:26 -0700 Subject: mb/google/deltaur: Configure GPIO B11 as PMCALERT GPIO B11 pin should be configured as PMCALERT function. This is required for the intergrated USB-C feature to work in the SOC BUG=b:154778458, b:156288164 TEST= build and boot coreboot image on deltan. Test Type-C port enumeration on Chrome OS Signed-off-by: Anil Kumar Change-Id: I8f995901b0a50d2c74f57aba96f86134c9d569e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41378 Reviewed-by: Tim Wawrzynczak Reviewed-by: Bora Guvendik Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/deltaur/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index aabfdc1239..432b9f88d8 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -76,7 +76,7 @@ static const struct pad_config gpio_table[] = { /* B10 : GPP_B10 ===> NC */ PAD_NC(GPP_B10, NONE), /* B11 : GPP_B11 ==> TBT_I2C_INT# */ - PAD_CFG_GPI_APIC(GPP_B11, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* B12 : GPP_B12 ==> SIO_SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PCH_PLTRST# */ -- cgit v1.2.3