From 7581730b65dab0b33b7e2eff7413780cc63c4791 Mon Sep 17 00:00:00 2001 From: Kapil Porwal Date: Fri, 8 Jul 2022 14:37:05 +0000 Subject: soc/intel/meteorlake: Use double digit GPIO pad numbers Google uses two digit GPIO pad numbers for internal GPIO references and Intel has updated their GPIO naming schemes too (see the GPIO implementation worksheet #641238) so use double digit GPIO pad numbers. Format - "GPP_%c%02d", gpio_group, gpio_pad_num e.g. GPP_A0 -> GPP_A00, GPP_V2 -> GPP_V02, GPP_C9 -> GPP_C09 etc. BUG=b:238196741 TEST=Able to build meteorlake based google/rex. Signed-off-by: Kapil Porwal Change-Id: Ieb7569c1a35b08c0970a604ec7b4b91e6179dd28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65719 Reviewed-by: Nick Vaccaro Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/mainboard/google/rex/variants/baseboard/rex/gpio.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/rex/variants/baseboard/rex/gpio.c b/src/mainboard/google/rex/variants/baseboard/rex/gpio.c index 70f05c49b1..8ddd6cece0 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/gpio.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/gpio.c @@ -7,19 +7,19 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* ToDo: Fill gpio configuration */ - /* H8 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - /* H9 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* ToDo: Fill early gpio configuration */ - /* H8 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - /* H9 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), }; const struct pad_config *__weak variant_gpio_table(size_t *num) -- cgit v1.2.3