From 743242b4aa3415769fc4f0e1ccdc13893aa2582d Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Fri, 16 Jun 2023 01:33:25 +0200 Subject: treewide,intel/skylake: Use boolean type for s0ix_enable dt option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Using the boolean type and the true/false macros give the reader a better understanding about the option. Thus, use the bool type for the attribute and use the macros for assignments. Skylake mainboards which use that option were changed by the following command ran from the root directory. socs="SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" && \ option="s0ix_enable" && \ grep -Er "${socs}" src/mainboard | \ cut -d ':' -f 1 | \ awk -F '[/]' '{print $1"/"$2"/"$3"/"$4}' | \ xargs grep -r "${option}" | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/${option}\".*\=.*\"1\"/${option}\" \= true/g" Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/75871 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) Reviewed-by: Jan Samek Reviewed-by: Mario Scheithauer Reviewed-by: Eric Lai Reviewed-by: Michael Niewöhner --- src/mainboard/acer/aspire_vn7_572g/devicetree.cb | 2 +- src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/atlas/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nami/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/rammus/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/soraka/devicetree.cb | 2 +- src/mainboard/protectli/vault_kbl/devicetree.cb | 2 +- src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 38a56cad77..1521501e70 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -311,7 +311,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # 11:8 in pwrmbase+0120h # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" # 11:10 in A4h-A7h register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" # 5:4 in A4h-A7h diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 74c601a58f..e19e2386b2 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -62,7 +62,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4c759f6d04..ee3c86bdc1 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -37,7 +37,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # Disable Command TriState register "CmdTriStateDis" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 2e3953ad4f..717ab547cd 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index aa905d105b..6a34241dc2 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 07363fd0c5..27a9bb9f50 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index b381a253a5..5f322b12e8 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -30,7 +30,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # Disable Command TriState register "CmdTriStateDis" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 8be97c8c36..bc2d4a0f8c 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -37,7 +37,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # Disable Command TriState register "CmdTriStateDis" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index a20c197537..fbe6c1f21d 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 4e4cbac04a..1f17fb1358 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -6,7 +6,7 @@ chip soc/intel/skylake register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" - register "s0ix_enable" = "1" + register "s0ix_enable" = true register "gpe0_dw0" = "GPP_B" register "gpe0_dw1" = "GPP_D" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index b4a08bf418..76f75800b3 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -20,7 +20,7 @@ chip soc/intel/skylake register "serirq_mode" = "SERIRQ_CONTINUOUS" # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch - register "s0ix_enable" = "1" + register "s0ix_enable" = true register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" -- cgit v1.2.3