From 73a9cf4ccb58eccb4a1383088f7c86f325fdad7f Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 21 Jul 2003 13:05:56 +0000 Subject: * update quartet target to latest SMP changes. * remove dead code from coherent_ht.c * add ldtstop code for link speed changes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/quartet/auto.c | 401 ++++++---------------------------- src/mainboard/amd/quartet/failover.c | 21 +- src/mainboard/amd/quartet/mainboard.c | 2 +- src/mainboard/arima/hdama/auto.c | 4 +- 4 files changed, 86 insertions(+), 342 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/amd/quartet/auto.c b/src/mainboard/amd/quartet/auto.c index 8395e12d6f..b773379dc6 100644 --- a/src/mainboard/amd/quartet/auto.c +++ b/src/mainboard/amd/quartet/auto.c @@ -1,225 +1,21 @@ #define ASSEMBLY 1 #include #include -#include "arch/romcc_io.h" +#include +#include +#include +#include #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "northbridge/amd/amdk8/early_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" - - -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\r\n"); - } -} - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\r\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); - } - } -} - -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -static void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - print_debug("\r\n"); - for(i = 0; i < 4; i++) { - unsigned device; - device = ctrl->channel0[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".0: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".1: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); - } - } -} - -#warning "FIXME move these delay functions somewhere more appropriate" -#warning "FIXME use the apic timer instead it needs no calibration on an Opteron it runs at 200Mhz" -static void print_clock_multiplier(void) -{ - msr_t msr; - print_debug("clock multipler: 0x"); - msr = rdmsr(0xc0010042); - print_debug_hex32(msr.lo & 0x3f); - print_debug(" = 0x"); - print_debug_hex32(((msr.lo & 0x3f) + 8) * 100); - print_debug("Mhz\r\n"); -} - -static unsigned usecs_to_ticks(unsigned usecs) -{ -#warning "FIXME make usecs_to_ticks work properly" -#if 1 - return usecs *2000; -#else - /* This can only be done if cpuid says fid changing is supported - * I need to look up the base frequency another way for other - * cpus. Is it worth dedicating a global register to this? - * Are the PET timers useable for this purpose? - */ - msr_t msr; - msr = rdmsr(0xc0010042); - return ((msr.lo & 0x3f) + 8) * 100 *usecs; -#endif -} - -static void init_apic_timer(void) -{ - volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000; - uint32_t start, end; - /* Set the apic timer to no interrupts and periodic mode */ - apic_reg[0x320 >> 2] = (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0); - /* Set the divider to 1, no divider */ - apic_reg[0x3e0 >> 2] = (1 << 3) | 3; - /* Set the initial counter to 0xffffffff */ - apic_reg[0x380 >> 2] = 0xffffffff; -} - -static void udelay(unsigned usecs) -{ -#if 1 - uint32_t start, ticks; - tsc_t tsc; - /* Calculate the number of ticks to run for */ - ticks = usecs_to_ticks(usecs); - /* Find the current time */ - tsc = rdtsc(); - start = tsc.lo; - do { - tsc = rdtsc(); - } while((tsc.lo - start) < ticks); -#else - volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000; - uint32_t start, value, ticks; - /* Calculate the number of ticks to run for */ - ticks = usecs * 200; - start = apic_reg[0x390 >> 2]; - do { - value = apic_reg[0x390 >> 2]; - } while((start - value) < ticks); -#endif -} - -static void mdelay(unsigned msecs) -{ - int i; - for(i = 0; i < msecs; i++) { - udelay(1000); - } -} - -static void delay(unsigned secs) -{ - int i; - for(i = 0; i < secs; i++) { - mdelay(1000); - } -} - +#include "cpu/k8/apic_timer.c" +#include "lib/delay.c" +#include "cpu/p6/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "debug.c" static void memreset_setup(const struct mem_controller *ctrl) { @@ -242,7 +38,6 @@ static void memreset(const struct mem_controller *ctrl) * */ - static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) { /* Routing Table Node i @@ -291,6 +86,8 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) return ret; } +#include "northbridge/amd/amdk8/cpu_ldtstop.c" +#include "southbridge/amd/amd8111/amd8111_ldtstop.c" #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -298,112 +95,38 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) #include "resourcemap.c" /* quartet does not want the default */ -#define NODE_ID 0x60 -#define HT_INIT_CONTROL 0x6c - -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) - -static int boot_cpu(void) +static void enable_lapic(void) { - volatile unsigned long *local_apic; - unsigned long apic_id; - int bsp; + msr_t msr; msr = rdmsr(0x1b); - bsp = !!(msr.lo & (1 << 8)); - if (bsp) { - print_debug("Bootstrap cpu\r\n"); - } - - return bsp; + msr.hi &= 0xffffff00; + msr.lo &= 0x000007ff; + msr.lo |= APIC_DEFAULT_BASE | (1 << 11); + wrmsr(0x1b, msr); } -static int cpu_init_detected(void) +static void stop_this_cpu(void) { - unsigned long dcl; - int cpu_init; + unsigned apicid; + apicid = apic_read(APIC_ID) >> 24; - unsigned long htic; + /* Send an APIC INIT to myself */ + apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); + apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT); + /* Wait for the ipi send to finish */ + apic_wait_icr_idle(); - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); -#if 0 - print_debug("htic: "); - print_debug_hex32(htic); - print_debug("\r\n"); + /* Deassert the APIC INIT */ + apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); + apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); + /* Wait for the ipi send to finish */ + apic_wait_icr_idle(); - if (!(htic & HTIC_ColdR_Detect)) { - print_debug("Cold Reset.\r\n"); - } - if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) { - print_debug("BIOS generated Reset.\r\n"); + /* If I haven't halted spin forever */ + for(;;) { + hlt(); } - if (htic & HTIC_INIT_Detect) { - print_debug("Init event.\r\n"); - } -#endif - cpu_init = (htic & HTIC_INIT_Detect); - if (cpu_init) { - print_debug("CPU INIT Detected.\r\n"); - } - return cpu_init; -} - - - -static void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg) -{ - outb(reg, port); - outb(value, port +1); -} - -static unsigned char pnp_read_config(unsigned char port, unsigned char reg) -{ - outb(reg, port); - return inb(port +1); -} - -static void pnp_set_logical_device(unsigned char port, int device) -{ - pnp_write_config(port, device, 0x07); -} - -static void pnp_set_enable(unsigned char port, int enable) -{ - pnp_write_config(port, enable?0x1:0x0, 0x30); -} - -static int pnp_read_enable(unsigned char port) -{ - return !!pnp_read_config(port, 0x30); -} - -static void pnp_set_iobase0(unsigned char port, unsigned iobase) -{ - pnp_write_config(port, (iobase >> 8) & 0xff, 0x60); - pnp_write_config(port, iobase & 0xff, 0x61); -} - -static void pnp_set_iobase1(unsigned char port, unsigned iobase) -{ - pnp_write_config(port, (iobase >> 8) & 0xff, 0x62); - pnp_write_config(port, iobase & 0xff, 0x63); -} - -static void pnp_set_irq0(unsigned char port, unsigned irq) -{ - pnp_write_config(port, irq, 0x70); -} - -static void pnp_set_irq1(unsigned char port, unsigned irq) -{ - pnp_write_config(port, irq, 0x72); -} - -static void pnp_set_drq(unsigned char port, unsigned drq) -{ - pnp_write_config(port, drq & 0xff, 0x74); } #define PC87360_FDC 0x00 @@ -464,48 +187,52 @@ static void main(void) .channel0 = { (0xa<<3)|12, (0xa<<3)|14, 0, 0 }, .channel1 = { (0xa<<3)|13, (0xa<<3)|15, 0, 0 }, }; - - + + if (cpu_init_detected()) { + asm("jmp __cpu_reset"); + } pc87360_enable_serial(); uart_init(); console_init(); - if (boot_cpu() && !cpu_init_detected()) { -#if 0 - init_apic_timer(); + enable_lapic(); + if (!boot_cpu()) { + stop_this_cpu(); + } + init_timer(); + setup_default_resource_map(); + setup_coherent_ht_domain(); + enumerate_ht_chain(0); + distinguish_cpu_resets(); + +#if 1 + print_pci_devices(); #endif - setup_quartet_resource_map(); - setup_coherent_ht_domain(); - enumerate_ht_chain(); - print_pci_devices(); - enable_smbus(); + enable_smbus(); #if 0 - dump_spd_registers(&cpu0); + dump_spd_registers(&cpu0); #endif - sdram_initialize(&cpu0); + sdram_initialize(&cpu0); #if 1 - dump_pci_devices(); + dump_pci_devices(); #endif #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 2)); + dump_pci_device(PCI_DEV(0, 0x18, 2)); #endif - /* Check all of memory */ + /* Check all of memory */ #if 0 - msr_t msr; - msr = rdmsr(TOP_MEM); - print_debug("TOP_MEM: "); - print_debug_hex32(msr.hi); - print_debug_hex32(msr.lo); - print_debug("\r\n"); + msr_t msr; + msr = rdmsr(TOP_MEM); + print_debug("TOP_MEM: "); + print_debug_hex32(msr.hi); + print_debug_hex32(msr.lo); + print_debug("\r\n"); #endif #if 0 - ram_check(0x00000000, msr.lo); + ram_check(0x00000000, msr.lo); #else -#if 1 - /* Check 16MB of memory */ - ram_check(0x00000000, 0x01000000); -#endif + /* Check 16MB of memory */ + ram_check(0x00000000, 0x01000000); #endif - } } diff --git a/src/mainboard/amd/quartet/failover.c b/src/mainboard/amd/quartet/failover.c index 017b03862f..8eeeaef7e1 100644 --- a/src/mainboard/amd/quartet/failover.c +++ b/src/mainboard/amd/quartet/failover.c @@ -2,22 +2,37 @@ #include #include #include +#include #include "arch/romcc_io.h" #include "pc80/mc146818rtc_early.c" #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" +#include "cpu/p6/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" static void main(void) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); + enumerate_ht_chain(0); /* Setup the 8111 */ amd8111_enable_rom(); - if (do_normal_boot()) { - /* Jump to the normal image */ + /* Is this a cpu reset? */ + if (cpu_init_detected()) { + if (last_boot_normal()) { + asm("jmp __normal_image"); + } else { + asm("jmp __cpu_reset"); + } + } + /* Is this a secondary cpu? */ + else if (!boot_cpu() && last_boot_normal()) { + asm("jmp __normal_image"); + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { asm("jmp __normal_image"); } } diff --git a/src/mainboard/amd/quartet/mainboard.c b/src/mainboard/amd/quartet/mainboard.c index 5690bd5afd..d93d2ed1d9 100644 --- a/src/mainboard/amd/quartet/mainboard.c +++ b/src/mainboard/amd/quartet/mainboard.c @@ -7,5 +7,5 @@ unsigned long initial_apicid[MAX_CPUS] = { - 0 + 0, 1, 2, 3 }; diff --git a/src/mainboard/arima/hdama/auto.c b/src/mainboard/arima/hdama/auto.c index 83f7598822..9ae459b136 100644 --- a/src/mainboard/arima/hdama/auto.c +++ b/src/mainboard/arima/hdama/auto.c @@ -77,11 +77,13 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) return ret; } +#include "northbridge/amd/amdk8/cpu_ldtstop.c" +#include "southbridge/amd/amd8111/amd8111_ldtstop.c" + #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" - static void enable_lapic(void) { -- cgit v1.2.3