From 717b6e3151b6ea42aaa4b1ab2a708e143d098878 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 17 May 2018 14:16:03 +0300 Subject: aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With implementation of LATE_CBMEM_INIT, top-of-low-memory TOLM was adjusted late in ramstage. We do not allow that with EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO space is now used with statically set TOLM. Also remove support code for the obsolete LATE_CBMEM_INIT this northbridge used. Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26585 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/aopen/dxplplusu/romstage.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index f79d3d3c92..6ea1261231 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -77,4 +78,6 @@ void mainboard_romstage_entry(unsigned long bist) } printk(BIOS_DEBUG, "SDRAM is up.\n"); + + cbmem_recovery(0); } -- cgit v1.2.3