From 6fb126773f538ea4467b1abfde6cb8c6fc3cc9bb Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 3 Jan 2022 18:49:35 +0000 Subject: soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` config The only option to make HECI1 function disable on Elkhart Lake SoC platform is using SBI under SMM mode. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727 Tested-by: build bot (Jenkins) Reviewed-by: Sheng Lean Tan --- src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb | 3 --- src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 3 --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 3 --- 3 files changed, 9 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index 18005418ef..0fdc88a7a8 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -12,9 +12,6 @@ chip soc/intel/elkhartlake register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 228bf60128..87b455fd83 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -12,9 +12,6 @@ chip soc/intel/elkhartlake register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index ca905576b0..acb928665e 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -12,9 +12,6 @@ chip soc/intel/elkhartlake register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" -- cgit v1.2.3