From 6deadeeeca7931807b2fc915d7ea263606f1a1e1 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 24 Aug 2021 11:45:39 +0200 Subject: mb/siemens/mc_ehl2: Disable SATA Port 0 This mainboard has only SATA Port 1 available with no device sleep feature. Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 21f462612a..062ac5ff83 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -87,7 +87,7 @@ chip soc/intel/elkhartlake # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "0" -- cgit v1.2.3