From 6dc9d0352e9c2dafb46c8c827d07cfdba2d744dd Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 16 Feb 2020 16:22:52 +0100 Subject: treewide: capitalize 'BIOS' Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/asus/p8z77-m_pro/cmos.layout | 2 +- src/mainboard/asus/p8z77-m_pro/early_init.c | 2 +- src/mainboard/google/cyan/Kconfig | 4 ++-- src/mainboard/google/link/mainboard.c | 6 +++--- src/mainboard/google/rambi/mainboard.c | 2 +- src/mainboard/intel/strago/Kconfig | 4 ++-- src/mainboard/kontron/ktqm77/mainboard.c | 6 +++--- src/mainboard/lenovo/t420/early_init.c | 2 +- 8 files changed, 14 insertions(+), 14 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout index da29d1c10e..4ac7b5d2eb 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -77,7 +77,7 @@ entries 421 2 e 8 usb3_mode # usb3_drv -# Load (or not) pre-OS xHCI USB3 bios driver +# Load (or not) pre-OS xHCI USB3 BIOS driver # 423 1 e 1 usb3_drv diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 800d975d0f..6c76a7ac29 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -115,7 +115,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */ + .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ .dimm_channel0_disabled = 0, /* Both DIMM enabled */ .dimm_channel1_disabled = 0, /* Both DIMM enabled */ diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 6331419cd3..94ffbc0bad 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -78,7 +78,7 @@ config VGA_BIOS_FILE depends on VGA_BIOS default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" help - The C0 version of the video bios gets computed from this name + The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run. @@ -87,7 +87,7 @@ config VGA_BIOS_ID depends on VGA_BIOS default "8086,22b0" help - The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1 config CBFS_SIZE diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 8be4012263..32e5487278 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -47,10 +47,10 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; - X86_CL = 0x00; /* Use video bios default */ + X86_CL = 0x00; /* Use video BIOS default */ res = 1; break; case 0x5f35: @@ -66,7 +66,7 @@ static int int15_handler(void) * bit 7 = LFP2 */ X86_AX = 0x005f; - X86_CX = 0x0000; /* Use video bios default */ + X86_CX = 0x0000; /* Use video BIOS default */ res = 1; break; case 0x5f51: diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index d4e38d0532..7e9b343880 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -48,7 +48,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; X86_CX = 0x0001; diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 5e710a52bf..640f5d4e91 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -35,7 +35,7 @@ config VGA_BIOS_FILE depends on VGA_BIOS default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" help - The C0 version of the video bios gets computed from this name + The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run. @@ -44,7 +44,7 @@ config VGA_BIOS_ID depends on VGA_BIOS default "8086,22b0" help - The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1 config EC_GOOGLE_CHROMEEC_BOARDNAME diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 2af5eb239f..5cd3fc4234 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -41,12 +41,12 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; X86_ECX &= 0xffffff00; - X86_ECX |= 0x00; /* Use video bios default */ + X86_ECX |= 0x00; /* Use video BIOS default */ res = 1; break; case 0x5f35: @@ -64,7 +64,7 @@ static int int15_handler(void) X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; /* Use video bios default */ + X86_ECX |= 0x0000; /* Use video BIOS default */ res = 1; break; case 0x5f51: diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 2e39885b6b..c675512d6f 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -48,7 +48,7 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 +// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: system port 4, OC0 */ { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ -- cgit v1.2.3