From 6db97a31ef26ae61ce95dc8df4c4a6e74386e5d4 Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Fri, 30 Jul 2021 17:25:38 +0800 Subject: mb/google/brya/variants/gimble: add TcssAuxOri Gimble don't have retimer on port0, the port need to be configured for the SOC to handle Aux orientation flipping. Also add "typec_aux_bias_pads" lets the SoC IOM firmware control the Aux DC bias voltages. BUG=b:195087071 BRANCH=none TEST=check both orientation can output display on type-c monitor. Signed-off-by: Scott Chao Change-Id: I057048c14110bb81bf5b5fd0e3151deb031ca5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56715 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 2 ++ src/mainboard/google/brya/variants/gimble/overridetree.cb | 2 ++ 2 files changed, 4 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index b8d0b5c173..aa72ae1725 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -3,6 +3,8 @@ chip soc/intel/alderlake device lapic 0 on end end + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + # GPE configuration register "pmc_gpe0_dw0" = "GPP_A" register "pmc_gpe0_dw1" = "GPP_E" diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index b658d20462..101e472d09 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -20,6 +20,8 @@ fw_config end end chip soc/intel/alderlake + register "TcssAuxOri" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port -- cgit v1.2.3