From 6489a19c780126a92931fc9b20a617cedbba7b6b Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sat, 18 Jul 2020 00:30:30 +0300 Subject: mb/asrock/h110m: undo set trig and bufdis for NF pads MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set this fields to 0. [1] Intel document #549921 [2] Intel document #336067-007US This is part of the patch set "src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ": CB:43455 - cedarisland: undo set trig and bufdis for NF pads CB:43454 - tiogapass: undo set trig and bufdis for NF pads CB:43561 - h110m: undo set trig and bufdis for NF pads CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG Change-Id: I6a6b745bdaacb1c4fbf032e4ce54cb25a72d790a Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/43561 Reviewed-by: Michael Niewöhner Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) --- src/mainboard/asrock/h110m/include/gpio.h | 168 +++++++++++++++--------------- 1 file changed, 82 insertions(+), 86 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 2a3b424b3c..193579c6a1 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -10,37 +10,37 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* GPP_A1 - LAD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), /* GPP_A5 - LFRAME# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* GPP_A6 - SERIRQ */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* GPP_A7 - GPIO */ PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), /* GPP_A11 - GPIO */ PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), /* GPP_A12 - GPIO */ PAD_CFG_GPI_INT(GPP_A12, NONE, PLTRST, OFF), /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ - PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* GPP_A14 - SUS_STAT# */ - PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - SUS_ACK# */ - PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), /* GPP_A16 - GPIO */ PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), /* GPP_A17 - GPIO */ @@ -68,7 +68,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B3 - GPIO */ PAD_CFG_GPO(GPP_B3, 1, DEEP), /* GPP_B4 - CPU_GP3 */ - PAD_CFG_NF_BUF_TRIG(GPP_B4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), /* GPP_B5 - GPIO */ PAD_CFG_GPI_INT(GPP_B5, NONE, PLTRST, OFF), /* GPP_B6 - GPIO */ @@ -88,11 +88,11 @@ static const struct pad_config gpio_table[] = { PAD_BUF(NO_DISABLE), PAD_PULL(NONE)), /* GPP_B12 - SLP_S0# */ - PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 - PLTRST# */ - PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF_BUF_TRIG(GPP_B14, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), /* GPP_B16 - GPIO */ @@ -110,35 +110,31 @@ static const struct pad_config gpio_table[] = { /* GPP_B22 - GPIO */ PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), /* GPP_B23 - PCHHOT# */ - _PAD_CFG_STRUCT(GPP_B23, - PAD_FUNC(NF2) | PAD_RESET(PLTRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | - PAD_BUF(RX_DISABLE) | 1, - PAD_PULL(20K_PD)), + PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - SMBCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_C0, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* GPP_C1 - SMBDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_C1, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* GPP_C2 - GPIO */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* GPP_C3 - SML0CLK */ - PAD_CFG_NF_BUF_TRIG(GPP_C3, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* GPP_C4 - SML0DATA */ - PAD_CFG_NF_BUF_TRIG(GPP_C4, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* GPP_C5 - GPIO */ PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - UART0_RXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), /* GPP_C9 - UART0_TXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C9, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), /* GPP_C10 - UART0_RTS# */ - PAD_CFG_NF_BUF_TRIG(GPP_C10, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), /* GPP_C11 - UART0_CTS# */ - PAD_CFG_NF_BUF_TRIG(GPP_C11, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), /* GPP_C12 - GPIO */ PAD_CFG_GPI_INT(GPP_C12, NONE, PLTRST, OFF), /* GPP_C13 - GPIO */ @@ -156,11 +152,11 @@ static const struct pad_config gpio_table[] = { /* GPP_C19 - GPIO */ PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), /* GPP_C20 - UART2_RXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C20, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), /* GPP_C21 - UART2_TXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C21, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), /* GPP_C22 - UART2_RTS# */ - PAD_CFG_NF_BUF_TRIG(GPP_C22, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), /* GPP_C23 - GPIO */ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES), @@ -176,13 +172,13 @@ static const struct pad_config gpio_table[] = { /* GPP_D4 - GPIO */ PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), /* GPP_D5 - I2S_SFRM */ - PAD_CFG_NF_BUF_TRIG(GPP_D5, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), /* GPP_D6 - I2S_TXD */ - PAD_CFG_NF_BUF_TRIG(GPP_D6, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), /* GPP_D7 - I2S_RXD */ - PAD_CFG_NF_BUF_TRIG(GPP_D7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), /* GPP_D8 - I2S_SCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_D8, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), /* GPP_D9 - GPIO */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, OFF), /* GPP_D10 - GPIO */ @@ -204,9 +200,9 @@ static const struct pad_config gpio_table[] = { /* GPP_D18 - GPIO */ PAD_CFG_GPI_INT(GPP_D18, NONE, PLTRST, OFF), /* GPP_D19 - DMIC_CLK0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D19, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_D19, 20K_PU, PLTRST, NF1), /* GPP_D20 - DMIC_DATA0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D20, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_D20, 20K_PU, PLTRST, NF1), /* GPP_D21 - GPIO */ PAD_CFG_GPI_INT(GPP_D21, NONE, PLTRST, OFF), /* GPP_D22 - GPIO */ @@ -216,37 +212,37 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - SATAXPCIE0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E0, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E0, 20K_PU, PLTRST, NF1), /* GPP_E1 - SATAXPCIE1 */ - PAD_CFG_NF_BUF_TRIG(GPP_E1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E1, 20K_PU, PLTRST, NF1), /* GPP_E2 - SATAXPCIE2 */ - PAD_CFG_NF_BUF_TRIG(GPP_E2, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E2, 20K_PU, PLTRST, NF1), /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E3, NONE, PLTRST, NF1), /* GPP_E4 - SATA_DEVSLP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E4, NONE, PLTRST, NF1), /* GPP_E5 - SATA_DEVSLP1 */ - PAD_CFG_NF_BUF_TRIG(GPP_E5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* GPP_E6 - SATA_DEVSLP2 */ - PAD_CFG_NF_BUF_TRIG(GPP_E6, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E6, NONE, PLTRST, NF1), /* GPP_E7 - GPIO */ PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, OFF), /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* GPP_E10 - USB_OC1# */ - PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* GPP_E11 - USB_OC2# */ - PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* GPP_E12 - USB_OC3# */ - PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), /* GPP_F1 - SATAXPCIE4 */ - PAD_CFG_NF_BUF_TRIG(GPP_F1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), /* GPP_F2 - GPIO */ PAD_NC(GPP_F2, NONE), /* GPP_F3 - GPIO */ @@ -274,11 +270,11 @@ static const struct pad_config gpio_table[] = { /* GPP_F14 - GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), /* GPP_F15 - USB_OC4# */ - PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* GPP_F16 - USB_OC5# */ - PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* GPP_F17 - USB_OC6# */ - PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* GPP_F18 - GPIO */ PAD_CFG_GPO(GPP_F18, 1, PLTRST), /* GPP_F19 - GPIO */ @@ -344,7 +340,7 @@ static const struct pad_config gpio_table[] = { /* GPP_G18 - GPIO */ PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), /* GPP_G19 - SMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), /* GPP_G20 - GPIO */ PAD_CFG_GPI_INT(GPP_G20, NONE, PLTRST, OFF), /* GPP_G21 - GPIO */ @@ -410,13 +406,13 @@ static const struct pad_config gpio_table[] = { /* GPD1 - GPIO */ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPD2 - LAN_WAKE# */ - PAD_CFG_NF_BUF_TRIG(GPD2, NATIVE, PWROK, NF1, RX_DISABLE, LEVEL), + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* GPD3 - PWRBTN# */ - PAD_CFG_NF_BUF_TRIG(GPD3, 20K_PU, PWROK, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), /* GPD4 - SLP_S3# */ - PAD_CFG_NF_BUF_TRIG(GPD4, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* GPD5 - SLP_S4# */ - PAD_CFG_NF_BUF_TRIG(GPD5, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* GPD6 - GPIO */ PAD_CFG_GPI_INT(GPD6, NONE, PLTRST, OFF), /* GPD7 - GPIO */ @@ -426,70 +422,70 @@ static const struct pad_config gpio_table[] = { PAD_BUF(TX_DISABLE) | 1, PAD_PULL(NONE)), /* GPD8 - SUSCLK */ - PAD_CFG_NF_BUF_TRIG(GPD8, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* GPD9 - SLP_WLAN# */ - PAD_CFG_NF_BUF_TRIG(GPD9, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* GPD10 - SLP_S5# */ - PAD_CFG_NF_BUF_TRIG(GPD10, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* GPD11 - GPIO */ PAD_CFG_GPO(GPD11, 0, PWROK), /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - DDPB_HPD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* GPP_I1 - DDPC_HPD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* GPP_I2 - DDPD_HPD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* GPP_I3 - DDPE_HPD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* GPP_I4 - GPIO */ PAD_CFG_GPI_INT(GPP_I4, NONE, PLTRST, OFF), /* GPP_I5 - DDPB_CTRLCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_I5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* GPP_I6 - DDPB_CTRLDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_I6, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I6, 20K_PD, PLTRST, NF1), /* GPP_I7 - DDPC_CTRLCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* GPP_I8 - DDPC_CTRLDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_I8, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I8, 20K_PD, PLTRST, NF1), /* GPP_I9 - DDPD_CTRLCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* GPP_I10 - DDPD_CTRLDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_I10, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I10, 20K_PD, PLTRST, NF1), }; /* Early pad configuration in romstage */ static const struct pad_config early_gpio_table[] = { /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* GPP_A1 - LAD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), /* GPP_A5 - LFRAME# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* GPP_A6 - SERIRQ */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ - PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* GPP_A14 - SUS_STAT# */ - PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - SUS_ACK# */ - PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), }; #endif -- cgit v1.2.3