From 62e784bd8a0049997e808cc4a944e08f478929ea Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Fri, 21 Apr 2017 15:54:44 +0200
Subject: nb/intel/pineview: Move to early cbmem
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

TESTED on D510MO.

Change-Id: I05aa40df0d2a090fcf734416669e9e1bbff094e4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19414
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/mainboard/intel/d510mo/romstage.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'src/mainboard')

diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index d39d2f6542..f99e185f2a 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -31,6 +31,8 @@
 #include <superio/winbond/common/winbond.h>
 #include <lib.h>
 #include <arch/stages.h>
+#include <cbmem.h>
+#include <romstage_handoff.h>
 
 #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
 #define SUPERIO_DEV PNP_DEV(0x4e, 0)
@@ -99,6 +101,8 @@ static void rcba_config(void)
 void mainboard_romstage_entry(unsigned long bist)
 {
 	const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
+	int cbmem_was_initted;
+	int s3resume = 0;
 
 	if (bist == 0)
 		enable_lapic();
@@ -131,4 +135,14 @@ void mainboard_romstage_entry(unsigned long bist)
 	ram_check(0x200000,0x300000);
 
 	rcba_config();
+
+	cbmem_was_initted = !cbmem_recovery(s3resume);
+
+	if (!cbmem_was_initted && s3resume) {
+		/* Failed S3 resume, reset to come up cleanly */
+		outb(0x6, 0xcf9);
+		halt();
+	}
+
+	romstage_handoff_init(s3resume);
 }
-- 
cgit v1.2.3