From 6296ae0258ede18087dfb1fed616a2335a4e3c77 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 15 Nov 2021 12:24:12 +0800 Subject: mb/google/brya: Move typeC AUX configuration to variant TypeC AUX configuration is variant specific. So move into variant level. BUG=b:205235144 TEST=No typeC port 0 AUX in felwinter. Signed-off-by: Eric Lai Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59290 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 2 -- src/mainboard/google/brya/variants/brya0/overridetree.cb | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index c89f24fde4..2204a71b70 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/alderlake - register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - # GPE configuration register "pmc_gpe0_dw0" = "GPP_A" register "pmc_gpe0_dw1" = "GPP_E" diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 0052d90a3a..bbba955e2d 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -43,6 +43,8 @@ chip soc/intel/alderlake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ -- cgit v1.2.3