From 60216355d21fae62daf00afa66443b03ed743e2a Mon Sep 17 00:00:00 2001
From: Eric Biederman <ebiederm@xmission.com>
Date: Sat, 23 Oct 2004 02:47:13 +0000
Subject: - With Xeon cpus it seems best to use the tsc calibrated with timer2
 as   the time source.  The apic timer also has a variable time base.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 src/mainboard/tyan/s2735/Options.lb | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/mainboard')

diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb
index cecb58bb9f..c68fd37489 100644
--- a/src/mainboard/tyan/s2735/Options.lb
+++ b/src/mainboard/tyan/s2735/Options.lb
@@ -78,6 +78,12 @@ default HAVE_HARD_RESET=1
 #default HARD_RESET_DEVICE=4
 #default HARD_RESET_FUNCTION=0
 
+##
+## Delay timer options
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
 ##
 ## Build code to export a programmable irq routing table
 ##
-- 
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