From 5c4783c205731410b1adee4c51b3019464ffbb3a Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 9 Sep 2021 16:14:01 -0600 Subject: mb/google/brya: Fix brya0 WWAN poweron sequencing The PCIe WWAN module used on brya0 requires control over 4 signals to successfully power it on. It is desirable to do this before passing control to the payload, because the modem requires a ~10 seconds initialization phase before it can be used. The corrected sequence looks like: 1) Drive device into full reset and enable power in bootblock 2) Deassert FCPO in romstage, after power rails stabilize 3) Deassert WLAN_RST#, then WLAN_PERST# in ramstage BUG=b:187691798 Change-Id: I10f15a4dcfd86216c334fb24b4693ea250d35ee4 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/57540 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- .../google/brya/variants/baseboard/brya/gpio.c | 8 +++++-- src/mainboard/google/brya/variants/brya0/gpio.c | 25 ++++++++++++++++------ 2 files changed, 25 insertions(+), 8 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 4c756291d7..c11cf42254 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -158,8 +158,7 @@ static const struct pad_config gpio_table[] = { /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ - PAD_CFG_GPO(GPP_E0, 1, PLTRST), + /* E0 : see end of E group */ /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ PAD_CFG_GPI(GPP_E1, NONE, DEEP), /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ @@ -206,6 +205,11 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L + NB. Driven high here so that it is sequenced after WWAN_RST_L; a + PERST# signal would normally be reset by PLRST#, but here it will be + explicitly programmed during a power-down sequence. */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index cd3509526b..6ca5e98d53 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -50,11 +50,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L */ + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), @@ -70,6 +70,8 @@ static const struct pad_config early_gpio_table[] = { /* Early pad configuration in bootblock for board id 2 */ static const struct pad_config early_gpio_table_id2[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ @@ -87,16 +89,16 @@ static const struct pad_config early_gpio_table_id2[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L */ + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated below) */ - PAD_CFG_GPO(GPP_F21, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ @@ -105,6 +107,11 @@ static const struct pad_config early_gpio_table_id2[] = { PAD_NC(GPP_H13, UP_20K), }; +static const struct pad_config romstage_gpio_table[] = { + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { const uint32_t id = board_id(); @@ -128,3 +135,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table_id2); return early_gpio_table_id2; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- cgit v1.2.3