From 5aa64b97db0577f4ba2e83b36fc41d33453cfb3d Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Fri, 9 Jun 2017 13:05:29 -0700 Subject: google/fizz: Enable cr50 over SPI By default disabled. Will need to add FIZZ_USE_SPI_TPM config to enable. BUG=b:62456589, b:35775024 BRANCH=None TEST=Reboot and ensure that TPM works in verstage CQ-DEPEND=CL:530184 Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/20134 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/fizz/Kconfig | 13 +++++++++++++ src/mainboard/google/fizz/devicetree.cb | 16 +++++++++++++++- src/mainboard/google/fizz/gpio.h | 29 +++++++++++++++++++++++++---- src/mainboard/google/fizz/mainboard.c | 6 ++++++ 4 files changed, 59 insertions(+), 5 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index da6e67465b..e160d7fc1d 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC + select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME @@ -28,6 +29,10 @@ config DRIVER_TPM_I2C_ADDR depends on FIZZ_USE_I2C_TPM default 0x50 +config DRIVER_TPM_SPI_BUS + depends on FIZZ_USE_SPI_TPM + default 0x1 + config GBB_HWID string depends on CHROMEOS @@ -65,6 +70,14 @@ config FIZZ_USE_I2C_TPM select MAINBOARD_HAS_I2C_TPM_CR50 select TPM2 +# Select this option to enable use of cr50 I2C TPM on fizz. +config FIZZ_USE_SPI_TPM + bool + default n + select MAINBOARD_HAS_SPI_TPM_CR50 + select SPI_TPM + select TPM2 + config TPM_TIS_ACPI_INTERRUPT int default 64 # GPE0_DW2_00 (GPP_E0) diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index abd5452f21..f1d2b7731a 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -181,6 +181,13 @@ chip soc/intel/skylake register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio + # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM + # communication before memory is up. + register "gspi[0]" = "{ + .speed_mhz = 1, + .early_init = 1, + }" + # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR # for TPM communication before memory is up. register "i2c[1]" = "{ @@ -259,7 +266,14 @@ chip soc/intel/skylake device pci 1d.3 off end # PCI Express Port 12 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 on end # GSPI #0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" + device spi 0 on end + end + end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1e.4 off end # eMMC device pci 1e.5 off end # SDIO diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index 9f7da49ed4..56324b54b0 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -80,10 +80,21 @@ static const struct pad_config gpio_table[] = { /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), /* PCH_SPI_H1_3V3_CS_L */ -/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), /* PCH_SPI_H1_3V3_CLK */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), /* PCH_SPI_H1_3V3_MISO */ -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), /* PCH_SPI_H1_3V3_MOSI */ +#if IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM) +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +#else +/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), +/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), +/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), +#endif /* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ /* GSPI1_CLK */ PAD_CFG_GPI(GPP_B20, 20K_PU, DEEP), /* VR_DISABLE_L */ /* GSPI1_MISO */ PAD_CFG_GPI(GPP_B21, 20K_PU, DEEP), /* HWA_TRST_N */ @@ -238,6 +249,16 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +#if IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM) +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +#endif #if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM) /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */ diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 5346276d35..1f6dc87c65 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -33,6 +33,12 @@ static void mainboard_enable(device_t dev) dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; /* Disable unused interface for TPM. */ + if (!IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM)) { + tpm = PCH_DEV_GSPI0; + if (tpm) + tpm->enabled = 0; + } + if (!IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM)) { tpm = PCH_DEV_I2C1; if (tpm) -- cgit v1.2.3