From 53ac68e5518472612c1c4b5adf40d068fa3d7dda Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 7 Apr 2020 23:37:11 -0700 Subject: mb/intel/tglrvp : Enable RP LTR BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40269 Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 ++++++ src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 501aa2a160..82303c6ddf 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -45,6 +45,12 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + # Enable RP LTR + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Hybrid storage mode register "HybridStorageMode" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 81d52a8d3d..043185bfdd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -45,6 +45,12 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + # Enable PR LTR + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Hybrid storage mode register "HybridStorageMode" = "1" -- cgit v1.2.3