From 51ab5e454d32c24d54e5ac2e5d23dd308fa953e5 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Mon, 20 Dec 2021 21:35:05 +0000 Subject: mb/starlabs/labtop: Enable I2C4 Enable unused I2C4 PCI device (00:19.0) so that UART2 (00:19.2) can be enumerated properly, using `PchSerialIoSkipInit` to prevent FSP-S from configuring anything regarding I2C4 (e.g. GPIOs). Signed-off-by: Sean Rhodes Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60264 Tested-by: build bot (Jenkins) Reviewed-by: Andy Pont Reviewed-by: Angel Pons --- src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index 35c201080b..2e001c6481 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -28,6 +28,7 @@ chip soc/intel/tigerlake # Serial I/O register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, }" register "SerialIoUartMode" = "{ @@ -165,7 +166,7 @@ chip soc/intel/tigerlake register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" end - device pci 19.0 off end # I2C4 + device pci 19.0 on end # I2C4 device pci 19.1 off end # I2C5 device pci 19.2 on end # UART #2 device pci 1c.0 off end # PCI Express Port 1 -- cgit v1.2.3