From 4fc59af03d0d76caa0b8497ea894f360c15c1a39 Mon Sep 17 00:00:00 2001 From: BryantOu Date: Wed, 15 Apr 2020 23:17:01 -0700 Subject: mb/ocp/tiogapass: Pull POST complete pin Tioga Pass platform use GPIO pin of GPP_B20 for POST complete, BIOS needs to configure this pin for BMC to poll, so it knows when to start to access other components. Tested=Read GPIO status (GPIOAA7) in OpenBMC, the value is 0, the command and result are shown as below, root@bmc-oob:~# cat /tmp/gpionames/FM_BIOS_POST_CMPLT_N/value 0 root@bmc-oob:~# Change-Id: I134f80153461c5acd872587038a2207586b658dd Signed-off-by: BryantOu Reviewed-on: https://review.coreboot.org/c/coreboot/+/40426 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/ocp/tiogapass/ramstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 8282eb09f4..16b4fd92e3 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -13,7 +13,18 @@ * GNU General Public License for more details. */ #include +#include +#include +#include void mainboard_silicon_init_params(FSPS_UPD *params) { } + +static void pull_post_complete_pin(void *unused) +{ + /* Pull Low post complete pin */ + gpio_output(GPP_B20, 0); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); -- cgit v1.2.3